Label every net, that way you can make shure you connected the right one.
Keep the "wires" straigt and short, there are many 90° bends in there that do not need to be there.
Something funky is going on at the output of IC3A, that junction should not be there.
Run the ERC to get possible problems.
JP2 has a missing connection on PIN4, my guess is, that should be that way.
You could Flip/Mirror components to minimise the wire cross routing, to me that makes it more readable but the downside is that the pins are not at the same location on every component.
For example, if you mirror IC3A along the horizontal axis, you can move IC5B over the junction between IC2A and IC3A.
The same for all the other gates down the line.
There are no decoupling caps in there, every IC should have one close to the supply pin on the PCB.
Upload the Eagle file next time along with the PNG
