Gated integrators (PPM demodulation)

[mark03]

I'm working on a free-space optical link intended for operation over 10-20 meters at a few hundred kbps.  For easy alignment, it will use a red power LED with a small/cheap collimating lens (around 20 degrees FWHM), and a red filter but no optics on the receiving end.  The numbers say it should work!

The transmit scheme of choice is PPM (pulse position modulation), in which each symbol period is divided into 2^N equal time slots, and N bits are transmitted by turning the LED on in one slot and off in the others.  If you are familiar with digital comms, you will recognize this as one example of M-ary orthogonal signaling, similar to some versions of OFDM, except in this case the orthogonality is between time slots rather than frequencies.  Neglecting switching losses and ultimate drive-current limits in the LED (i.e. a first-order analysis), performance goes up as the modulation order is increased, because the LED has an average-power constraint but no peak-power constraint.

Ok, so that is all well and good, I've satisfied myself that I can modulate the LED at > 1 MHz with decent rise/fall times, and I am using Phil Hobbs' excellent optics book to design the photodiode front-end.  But I've gone back and forth somewhat on the subsequent signal-processing and MCU interface.  I was initially going to sample the raw signal at ~ 4 MSPS, but then I decided to try a gated-integrator approach instead.  (This is just a matched filter, where the integration time is equal to one of the PPM timeslots.)  This is well outside my analog comfort zone, so I'm hoping to get some feedback.

Here is the PD frontend and gated-integration circuit as it stands:



(Edit: added full PDF schematic below because the PNG may be difficult to view in a browser window)

The integrators are meant to operate in ping-pong style, with output samples taken alternately on the MCU ADC channels 5 and 6.  The INT_x and RESET_x control signals will be generated with the aid of MCU timers; all of the jumpers near the MCU are for ensuring maximum flexibility in that regard.  The integrators (U8) run from +/- 5V supplies.  U5 runs from a single 3.6V supply shared with the MCU analog rail, and serves to place the outputs into the necessary 0-3.6V range for the ADC.

Design criteria for the integrators were as follows (using component references from the top branch):
1) Saturate to +/- 5V output for any input averaging +/- 0.5V over a PPM time slot (1 us) => R27 * C26 = 0.1 us.
2) Minimize the CMOS switch charge injection but keep its Ron * C26 << the PPM time slot (1 us) so  there is time to reset.
3) Don't let R27 get too small, so as to present a reasonable load to the ADA4817 front-end stage.
4) Don't let C26 get too small either, so as to minimize charge-injection effects (but the resulting offset should be the same on every cycle).

Does this sound about right?  Any traps I've failed to notice?

The ADG611 switches have Ron ~ 60 ohms, so there will be a significant voltage drop across the INT_x switches during integration.  But Ron looks to be relatively flat in the region of 0V, and this being a communications link, mild distortion is not a concern.

BTW, the combined offsets of the cascode (Q7) bias R33 and ambient light will be countered with an adjustable Vbias+ supply under MCU control.  Software will run a slow control loop to adjust Vbias+ between about 11-34V until the front-end output is close to centered.  Vbias- is -25V; both of these supplies come through "capacitance multiplier" stages.