Does the sensor even have AGnd and DGnd pins? If not, I wouldn't even consider it as a option.
Plus rather than trying to isolate noise and ground bounce, eliminate the source. What is the maximum rise/fall times for the digital inputs? What's the input capacitance? Either drive them with a slew-rate controlled driver, or add series resistance that increases the rise/fall times to close to the maximum, with a comfortable margin for tolerance and variation in the ICs, while maintaining setup and hold times required.
Also, if you can do it, use synchronous sampling to avoid sampling your low noise analog while you are fiddling with the digital IOs. Assuming the imaging chip is clocking out different analog pixels, why would you even be sampling before the clock edge is even settled? From the clock edge, to a propagation delay, to a settling time on the output, amp, and ADC, if the clock signal isn't ringing, it should be settled and in a static DC state.
Splitting ground planes and not causing more problems for yourself than you solve requires every return current and current loop to be accounted for. Both low-frequency ones following least resistance, and higher frequency ones following least impedance. It can be done with success, but personally, I avoid it unless I have very good reasons to.