Help with a misbehaving LDO

[theworldbuilder]

I have a 5V -> 3.3V LDO that is misbehaving while in circuit. (Link to the LDO product page: https://www.ti.com/product/TLV755P)

While in circuit the LDO was regulating the 5V input down to a 3.7V output. Way outside of spec.
When I desoldered the LDO from the board and fly wired it into a breadboard it regulated a 5V input down to exactly 3.3V.

This would point me at the circuit board being the issue. The symptoms seem to look like some kind of grounding issue to me.
So I soldered on another LDO and added a bodge wire from the LDO ground to the circuit ground and checked the output voltage.
Still regulating to 3.7V.

I also tried shorting the EN input to ground to disable to output of the LDO. This only caused the LDO output to drop from 3.7V down to 3.5V. Not good!

There's something wrong with the circuit/layout and I can't put my finger on it. Could anyone help me out here? I'd really appreciate it!

I've attached images of the LDO circuit and the PCB layout below.
I anyone is still willing to trust .zip files from strangers I've also attached a stripped down version of the project.

[CJay]

Have you used the capacitor types specified by the datasheet (X7R, X5R ceramics) and why have you got a capacitor on the EN pin?

[SmokedComponent]

Scope the output and see if that 3.7V is even DC, maybe it is oscillating.

[theworldbuilder]

Have you used the capacitor types specified by the datasheet (X7R, X5R ceramics) and why have you got a capacitor on the EN pin?

Thanks for the reply!

Yeah the capacitors are of type X5R, and the capacitor is on the enable pin to delay the power on of the 3.3V line. It's to do with the power sequencing of the FPGA.

I thought myself that this cap might have been causing a problem so I removed it and made no difference.

[theworldbuilder]

Scope the output and see if that 3.7V is even DC, maybe it is oscillating.

Thanks for replying!

I've already scoped up the 3.7V volts and there wasn't a single oscillation to be found unfortunately.

I have also tried the board with different voltage inputs and the only time the LDO output is anywhere near 3.3V is when I start dropping the 5V input down to the point that I'm nearly reaching the drop out voltage threshold.

[magic]

there wasn't a single oscillation to be found

Weird.
And you are measuring right at the pins of the LDO chip, right?
And you are sure the pinout is right?

Maybe bodge 100nF cap between GND and Vin close to / right on the package, if there isn't one already.

[georges80]

Possibly something is backfeeding the 3.3V rail (pullup to 5V or something else on the board). Is the rest of the board populated?

Remove the regulator and feed it from your kludged 3.3V external circuit to test?

cheers,
george.

[CJay]

Have you used the capacitor types specified by the datasheet (X7R, X5R ceramics) and why have you got a capacitor on the EN pin?

Thanks for the reply!

Yeah the capacitors are of type X5R, and the capacitor is on the enable pin to delay the power on of the 3.3V line. It's to do with the power sequencing of the FPGA.

I thought myself that this cap might have been causing a problem so I removed it and made no difference.

Still bugging me, did you pull the EN line up by bypassing the 10K?

Also, as Georges80 says, is there voltage on the output with the input isolated?

[theworldbuilder]

there wasn't a single oscillation to be found

...

Maybe bodge 100nF cap between GND and Vin close to / right on the package, if there isn't one already.

Bodged one in and no difference unfortunately

Yeah the correct pins are being measured and I'm using the right pinout. Double triple checked those

[theworldbuilder]

Possibly something is backfeeding the 3.3V rail (pullup to 5V or something else on the board). Is the rest of the board populated?

Remove the regulator and feed it from your kludged 3.3V external circuit to test?

cheers,
george.

This was something I didn't think of.

After doing some tracing back the only thing I could find that could be connecting the 3.3V rails to the 5V rail are the level shifters.

After going back over the datasheet I'm only more suspicious and confused.
Nexperia's datasheets are absolute raging garbage fires in my opinion. Every time I come across them in work my skin crawls.

For anyone wanting to look at this themselves here is a link to the data sheet: https://www.mouser.ie/datasheet/2/916/LSF0108-1664472.pdf (Mouser was the quickest place to find it)

It looks like the device might be driving between refA and refB but I'm not sure how to interpret the datasheet diagrams and the datasheet doesn't make and mention of it.

Unfortunately I won't have the time spin up another board for quite a while.
But when I get the chance the first thing I am doing is populating the board without these level-shifters.

Anyone else have thoughts on this?

I have also attached an image of one of the level shifter circuits:

[theworldbuilder]

Have you used the capacitor types specified by the datasheet (X7R, X5R ceramics) and why have you got a capacitor on the EN pin?

Thanks for the reply!

Yeah the capacitors are of type X5R, and the capacitor is on the enable pin to delay the power on of the 3.3V line. It's to do with the power sequencing of the FPGA.

I thought myself that this cap might have been causing a problem so I removed it and made no difference.

Still bugging me, did you pull the EN line up by bypassing the 10K?

Also, as Georges80 says, is there voltage on the output with the input isolated?

I didn't bypass that 10K but I did measure the voltage on the side connected to the LDO and it was a rock solid 5V.

[CJay]

If it's not oscillating and the EN line isn't doing 'weird' stuff then without having hardware in front of me to prod and probe I'm kinda out of ideas other than Georges80 suggestion.

FWIW, if you suspect the LSF0108 the TI datasheet may be better than the Nexperia one, contains a *lot* more info and links to plenty of design detail about biasing which might be useful.

https://www.ti.com/product/LSF0108#tech-docs

[theworldbuilder]

If it's not oscillating and the EN line isn't doing 'weird' stuff then without having hardware in front of me to prod and probe I'm kinda out of ideas other than Georges80 suggestion.

FWIW, if you suspect the LSF0108 the TI datasheet may be better than the Nexperia one, contains a *lot* more info and links to plenty of design detail about biasing which might be useful.

https://www.ti.com/product/LSF0108#tech-docs

I don't know why it never crossed my mind to check for a TI datasheet. Thank you very much!

After some reading it looks like I have found my problem. Current needs to pass from RefB into RefA, and my poor little LDO can't sink current. This I think is the issue!

Thank you all for your input!
Hopefully I'll be able to come up with a way around this so that I can still use my boards while I redesign them in the mean time to remove this error I made.
Any ideas for a current sinking/sourcing voltage source?

[julian1]

In the pcb pic, the gnd fill looks like an isolated island. So presumably one of the vias re-connects it with board gnd? There's also a blue line coming from one of the vias, which could indicate a disconnected net. It's hard to tell from the pic, but maybe worth checking if you haven't already.       

[exmadscientist]

Nexperia's datasheets are absolute raging garbage fires in my opinion. Every time I come across them in work my skin crawls.

Funny, I feel the same way about auto-bidirectional level shifters!

Unless you are using the automatic bidirectional functionality, I strongly suggest you design out that part. Their biasing requirements are a little fussy but can be accommodated. The bigger issue is that they are very susceptible to noise: it is very easy for a small glitch on one line to flip its direction, causing output driver contention and possible damage. In my experience, the only time they are ever appropriate is for a true bidirectional signal with no direction signal. Some ADI ADCs use such a protocol for configuration; this is a mistake, but one you just have to design around.

The warning in TI's datasheet, §9.2.1.2.1 (yes, really ) is instructive; emphasis in original:

If either output is push-pull, data must be unidirectional or the outputs must be tri-state and be controlled by some direction-control mechanism to prevent HIGH-to-LOW bus contention in either direction. If both outputs are open-drain,no direction control is needed.

If all you need is fixed- or programmed-direction translation, there are several such ICs in the '244 family and others that will do it. If you have a common bus such as I²C or SPI, again, there are ICs for that. And if you do need to keep this craptacular device (as, sometimes, one must), I suggest fixing up the symbol. There's no real reason to have A8 and B8 separate, or A7 and B7 misaligned.

Loads can be achieved with a zener (crummy regulation), zener reference (TLV431 and friends), true source-sink supply (rare in LDOs -- often used for DDR termination, you may have some luck there; sync buck switchers can do it), or, if you know the maximum current to sink, just a humble resistor. Many or most designs get away without any additional load, because there is enough base load on the rail to just absorb the current.

[theworldbuilder]

In the pcb pic, the gnd fill looks like an isolated island. So presumably one of the vias re-connects it with board gnd? There's also a blue line coming from one of the vias, which could indicate a disconnected net. It's hard to tell from the pic, but maybe worth checking if you haven't already.     

Yeah that's just a line indicating the part number on the silkscreen, good spot though I never noticed this before.

[theworldbuilder]

Nexperia's datasheets are absolute raging garbage fires in my opinion. Every time I come across them in work my skin crawls.

Funny, I feel the same way about auto-bidirectional level shifters!

How about we call it even? Both Nexperia's datasheets and auto-bidirectional level shifters are raging garbage fires!

But really thanks for your comment, some good information in there!

I've already started coming up with a way to switch to using one programmed-direction level shifter and another uni-directional level shifter.
I think I have an idea of how to implement it using the RD signal to control the DIR and the CS signal to control the OE.
But if push comes to shove I may simply have to pull the level shifters off entirely. I hope it won't have to come to that but it wouldn't be awful either.

[pigrew]

Hmm, these auto-directional level shifters are kooky, though I'm sure they'll work well (for slow signals). (EDIT: With very strong pull-ups, they can work for fast signals, too)

I believe that you are missing a 200kohm resistor between your supply and the EN & REF_B pins of your level shifter. The capacitor can remain, but EN needs to be directly tied to REF_B.

Without it, your 3.3V is being shorted to to 5V-(Vt). Vt is a n-MOSFET threshold voltage. (EDIT: There may also be ESD double-diodes on the I/O pins which would clamp things within a diode drop of the supply voltage... it's unclear from the datasheet if they are there.)

A TI appnote (slva675b) describes what to do.

The low side supply also has to be able to sink about 10 uA of current. You could accomplish this by adding a 200k resistor from 3.3V to GND