High speed clock problem with custom CMOS chip

[robint91]

Hi all,

I'm tackling a problem for a while now. We have gotten a custom 40nm CMOS chip (university stuff,) which has a clock input to read out some data, fairly low speed stuff. The clockrate is 10MHz maximum. Currently I'm trying with a xilinx fpga(Artix 7) to readout that chip. So it starts, this thing has only tested with very fancy measurement equipment, like a Tektronix AWG7000. It is a 12GSPS AWG with outputs that have a rise/fall time of 35ps. Which passed the tests of reading that low speed buffer. We used other equipment with similar specs, it also works. The chip has ODT of 50 Ohms.

The chip has his IO rail on 0.9V VDD. So to translate the voltage form 3.3 Volt logic to 0.9 I use a GTL2003. Which I also used for other projects. Here are the problems starting, we see that the chip is clocking to much. In other words we put in 64 pulses a counter says 65 or 66. If I view the signal on the oscilloscope I see a nice monotonic rising signal and with the GTL2003 I get rise times of 100ns. This doesn't work....

Then I tried some high speed comperator with rise/fall times lower as 10ns. Almost no improvement on the clocking thing.

Then I build my own digital inverter with RF NPN/PNP transistors, I got around 2ns. Nothing....

I hacked the logic levels of LVPECL logic to give me a signal between 0 Volt and 0.9 Volt. It did something, rise times are now somewhere around 500ps single ended

What helps is to shift the DC point of the IO signal to -0.3Volt for low and 0.8Volt for high. This is for some PMOS transistors that are too weak.

The chip has NO schmitt trigger at the input. Combined that with high speed cmos tech it is giving me a bad time. The input is simulated until 6 GHz. That thing is fast enough to glicht at every noise at the bondpad. If you add that with a slower rise time, "glitches a volonté".

Now my question is does somebody know of a circuit/module/chip that can generate the following:
Vol: -0.3V (adj)
Voh: 0.8V (adj)
trf: below 100ps

I know this is a long shot but let's try it anyway.

[Rerouter]

you would probably be looking for a clock distribution chip, that is where most of the fast rise time solutions end up, especially as its 50 ohm,

[robint91]

@Rerouter, did that already with the LVPECL logic chips. But it is pain to get the correct levels, most of them are like 1.8/2.4 Volt levels. But not the cmos levels I need.

[AndyC_772]

we see that the chip is clocking to much. In other words we put in 64 pulses a counter says 65 or 66. If I view the signal on the oscilloscope I see a nice monotonic rising signal and with the GTL2003 I get rise times of 100ns. This doesn't work....

You're describing absolutely classic symptoms of poor impedance matching. What happens is:

- fast edge is launched by the driver into a transmission line, which could be a PCB trace, a wire, or the lead frame of an IC... or some combination of them.

- the edge arrives at the receiver, which causes the device to clock.

- because the receiver isn't correctly terminated with the characteristic impedance of the transmission line, the wave reflects off the receiver and starts travelling back up the transmission line towards the transmitter again.

- it then bounces off the transmitter, and travels back towards the receiver again. When it arrives at the receiver for the second time, depending on the relative magnitudes of the incident and reflected waves, and the 0/1 threshold at the receiver, it can cause a second clock transition.

This is a very well understood topic, and there's a set of 'rules of thumb' which will help you get the circuit working even if you don't have access to a proper high speed simulation package. You need to fully understand series and parallel termination, the concept of a characteristic impedance, and the importance of a solid, unbroken ground plane on your PCB.

Once you've researched these topics, you should have a feel for the numbers too. It's all but impossible to actually see these effects with a scope, and once you consider the effect of the scope probe's capacitance, the reason why should become obvious.

[robint91]

You're describing absolutely classic symptoms of poor impedance matching.

That is the whole point the receiver is fully terminated with the correct impedance. The tracks are 50 Ohm on the PCB and it has a on chip 50 termination resistor. I have tried to do some series termination 10 to 50 Ohm. It doesn't change much.

Also what I did was coupling the fancy AWG to the chip and played with the rise time of the signal. If I go lower to 500ps it works, no double clocking. If I go higher for example 5ns, I see double clocking.

I think this tells me that it isn't a termination issue. And I don't see any reflections when I probe with a +1GHz bandwidth probe + scope.

[AndyC_772]

Ah, OK then. (I'll leave my post above in case anyone else experiences similar symptoms in another context).

If slower edges are more problematic, then it's possible you have a combination of very high bandwidth but poor noise margins at the receiver. A slow edge with superimposed random noise can cause multiple clock transitions, because the peaks and troughs of the noise take the input alternately above and below the threshold.

Your logic levels are very low. Do you know where the 0/1 threshold actually is?

[kevinvinv]

HI,   My first thought too was that of an impedance mismatch but maybe not.   

Can you post any photo's of the waveform at the receiving end?   Not trying to point any fingers but how careful are you being with the probing technique?   For something like this  (~1nS) I would not use ANY sort of alligator ground clip or anything of that nature.   Need to probe with the tightest of ground connections using a special adapter for the probe.

Just my .02

[robint91]

AndyC_722, that is exaclty what is happening. Now if we have a edge steep enough than the noise margin increases. I think there is only like a few milivolts of hysteresis (maybe even lower)
The logic levels are normal for 0.9 Volt logic, but I guess that the threshold is around 400 mV.

Kevinvinv, I'm very careful when probing it. I did already do fancier stuff as this.

In the end, I need to generate this steep edge with the correct voltage levels. I have NO idea how to do it....

[nctnico]

I think this tells me that it isn't a termination issue. And I don't see any reflections when I probe with a +1GHz bandwidth probe + scope.

This could be noise induced switching. Who designed the input? Perhaps you could run simulations on the design for the input and see how sensitive it is too noise. An IC designer once told me that designing the input and output pads of a chip is a bit of an art in its own. If there is no hysteresis at all on the input you may want to considering doing a respin.

[T3sl4co1l]

Lesson learned, limit bandwidth everywhere possible... even on die, it seems!

I'm curious about the implications of your logic thresholds.  Why should it need V_IL = -0.3V?  Is the PMOS not being turned on sufficiently?  Was this a fab error, or is it perhaps a consequence of incorrect supply voltage?  Does it operate at Vcore = 1.2V, perhaps?

Tim

[Marco]

ADCLK914 has 1.9V swing with 100 ps tr.

[w2aew]

If that Tek AWG7000 doesn't have the interleave output, or the high-speed output option, then it has a few switchable low-pass filters that you can stick in series with the output signal using the channel setting panel.

[AndyC_772]

The logic levels are normal for 0.9 Volt logic, but I guess that the threshold is around 400 mV.

Can you check this?

I once worked with an IC which was an early prototype, and although it was designed to have 3.3V I/O, the logic threshold between 0 and 1 was down around 0.4V or thereabouts due to a design error in the chip. We never got it to work reliably.