rstofer
Some people think that a RISC machine is simpler then a CISC machine.
I look at that statement as a loaded question.
For example, Today I see most designs being based on a fixed clock.
This changes what is possible in a design.
The PDP-11 is not a Fixed Clock machine.
The microcode has a field that selects what delay is needed for each microcode step!. In place of one fixed in time critical path time, you have many different times.
The PDP-11 uses a delay line as it's clock source. The selected output of this delay line becomes the next input to the delay line.
With this, you can have a microcode step where the microcode address change is the critical path time and have a critical path that adds the delay of the 181 for a second critical path time.
CPU logic is still clocked logic but clock is not a fixed time length but in many fixed time delays.
So a small change can change the design rules.This change also lets microcode do more with less logic by using more steps.
Adding Rows & bits to microcode can be a lot cheaper for chip count then adding a bunch of logic.
To restate What I have said
The PDP-11 makes 8 registers visible to the ISA.
The PC one of the 8, is made into the PC Register by Different microcode.
Any one to the 8 registers can be a Stack Register. It's the microcode that connects the PUSH/POP instructions to the stack register.
To Make logic in CPU simpler 16 registers are used internal to CPU
The Address bus, Data bus, control bus & IR register are some of the hidden 8 registers.
So should you look at MIPS if your are building with TTL chips and not a CHIP where you have many transistors?
Microcode with micro sequencing, you can build a CPU with a lot less chips and use the 181 ALU many places for it's math & logic reducing chip count more..
From a Teaching point of view, starting from very simple that works with options to add more parallel processing later would be easer to teach.
Figure 2.4.6 shows a separate adder using to form microprogram_counter + 1. I don't know (yet) is the counter could be implemented as a counter/register.
With micro sequencing, you can use the one ALU to add to the PC while instruction fetch is happening.
As I see it, if you are building from TTL chips, less chips is easer to build and teach.
Using a register file where possible is much less chips then having many registers with many inputs & outputs.
If the CPU is built around an ALU based on the 181, it is smart to use the 181 as much as possible.
Need to keep in mind that LC3b is a 32-bit RISC CPU.
That video linked above is well worth the time.
I would certainly be more interested in this design as a learning tool than in some truly hairy CPU like the Z80.
Hairy Z80
Are you comparing apples to oranges?
An 8-bit base instruction set size has a lot of limits due to being 8-bits wide.
Think you would find that Z80 in microcode with micro sequencing is very simple.
The base instruction set is the 8080 where
D7, D6 is and instruction field used to select 4 groups of instructions.
D5,D4,D3 and D2,D1,D0 are two octal based fields.
The instruction set is simple when you use octal to look at instructions.
What Z80 added to 8080 instruction set is also simple & logical.