In the same circuit how much can Vbe vary for different small-signal transistors

[741]

According to Ebers-Moll, there is this factor "Is(T)": the saturation current at temperature T. This is device-dependent.

I have no feel at all for how much Is(T) varies across the spectrum of "typical small-signal transistors", and also I never know what is a sensible guess for Vbe. The 0.65V figure seems to be lower than that I see - either for real or in simulations.

Yes, a design which relies on Vbe having an exact value is a bad design - but even so, I'd like a feel for this.

In the present case, my question is this (ignoring temperature effects for now at least): How much real-world variability (due to Is(T) spread) can I expect from a 3v3 supply PNP current source where the collector has to be about 2v5 at 40mA? There is little 'headroom' across the emitter resistor, which I have at about 15 Ohms, and a load of 60 Ohms.

I'm wondering about device-to-device spread in  Is(T) at some fixed temperature.

For instance, how much does Is(25 C) vary between devices?

[741]

I just gathered some example data, the spread can be large, see the 2N2222A by ST, shown as 0.6(min) to 1.2(max) under the same test conditions 

That can't be used as a basis for designing a current source, surely?

Many DS just show one curve (eg for collector current against typical Vbe), leaving me guessing about "device-to-device spread" under fixed external conditions.

[chilternview]

I expect most of that variation (0.6-1.2v is due to base resistance variability. At Ib=15mA, that's a lot of base current and so Ib * Rbb will be significant. Use a low Ib and the exponential term of the diode current equation will dominate.

[T3sl4co1l]

"Sat" means saturated i.e. hFE is low and gm is nonexistent; Ebers-Moll doesn't apply in this regime.

Also do you really want to use a datasheet as old as 2N2222?  Those data were drawn up in 196x, broad enough to fit anything manufacturers were willing to sell under the JEDEC designation.  The datasheet doesn't really represent any particular part, or even family or process.

Not that you'll have better representation with newer and proprietary parts' datasheets, but moreso for other reasons (actual device variability, give or take some guard band to optimize yield, or ease of testing).

Under same Ic and Vce (non saturated), I think you'll find a given part varies less than 100mV, but you'll have to test over many makes and production dates to know for sure.

I surveyed a few 2N3904s from my bin, once, but I don't recall what the spread was, maybe 20 or 30mV?  Think I did that just to bin a few for some diff amp I was building, and within a few mV was fine (sample size, ~couple dozen).

Tim

[741]

Thanks for the clarification/reminder about Ebers-Moll not applying for "Saturated" (in the sense of "fully-on").
[ Of course, a potential nomenclature conflict is that I_s is the reverse saturation current ]

OK So in that case then I have no data at all on device spread from the data-sheets.

I'm still interested to have a feel for the extent to which "Vbe" (as a value used for circuit design) will vary though.

[741]

In the simulation, at low Ib, I see large circuit variation in Ic with temperature. That gets much less with a low source impedance. I am assuming the drop across the (external) input resistance is responsible for that.

[T3sl4co1l]

With respect to temperature, for a given part, expect say 0.4 to 0.8V, from a 0.6-0.7V typical Vbe, over commercial temperature range.

What are you designing?  Saturated switches?  Amplifiers?  Exponentiation and other analog arcanum?

Tim

[vk6zgo]

In earlier times, it was considered good design to produce circuitry which was to the greatest extent possible immune to variations in device characteristics.
This was an important consideration with vacuum tubes, & to an even greater extent in the early generations of semiconductor devices.

[jonpaul]

Worst case scenario design and Fail Safe
are used in good engineering designs, and apply for all technology, not just discret transistors.

Many circuits have feedback or a balanced pair to accommodate wide,variations in semiconductor parameters.

Jon

[Terry Bites]

I'm still in those times, always aiming to design out the variables. I worry that this may be becomming a lost art.

[magic]

BC547 appears to guarantee 0.55~0.7V for 2mA at 25°C.

0.6~0.65V is the typical result of testing small BJTs with DMM diode mode, between E and B-C shorted together.

[jonpaul]

besides Ebers-Moll model, 1950s BTL,  try the more recent Gummel-Poon model from 1970, also at BTL.

https://en.m.wikipedia.org/wiki/Gummel-Poon_model

Jon

[MathWizard]

I've been listening to these for a while, but I don't follow along trying the equations yet.


I went back and watched some solid state chemistry lectures too. For learning about valence and conduction bands, and Fermi-distributions.

[chilternview]

"Sat" means saturated i.e. hFE is low and gm is nonexistent; Ebers-Moll doesn't apply in this regime.

It's still a (forward biassed) PN junction, with a series resistance which becomes important at high current (ok call it saturation if you will, but you can see the same effect in just a diode).

The Is term in the classical model is dependent on emitter area, the square of the intrinsic carrier concentration and the base Gummel number which is a measure of the total charge in that region. And that depends on the B-E junction depth, for diffused devices this will be the main source of variability.

If you want a more device-independent reference you need to eliminate that variable e.g. by using the difference between two devices (e.g. like a bandgap reference).

[741]

I was only wanting to design a simple current source to deliver about 40mA. I want to be within 10%.

Ignoring temperature, which can be compensated for, I can't put a sensible figure on how device-specific variation in Vbe could affect things.

At a specific temperature then, say 20C, can I say "the circuit will be within 10%" -  or do I always need a caveat "assuming typical Vbe values"?

Note I'd like a discrete solution for speed. I've been assuming a standard "resistor in series with emitter sets the current" design.

[magic]

You want 40mA through 15Ω, so 600mV.
Assuming you can use 1% resistors, voltage drop must be accurate to 9% or ±54mV.
Hence Vbe must be consistent to the same level. (Or better, if you 1.3V reference isn't ideal too).

Maybe doable if you stick to one type, preferably with low base resistance (which effectively appears in series with the emitter resistor, divided by β).
Some 2N2222 or better 2N4401 because I'm sure the 2222 haters will crawl out in a moment and scream at me.

But I don't design manufacturable products for a living so I can say whatever I want without consequences

I don't think any discrete transistor manufacturer guarantees this level of consistency, so yes, you are ass-uming typical characteristics.

edit
BTW, there are some "analog LED driver current source" chips, maybe one of those could work?

[T3sl4co1l]

FWIW, I've seen quite consistent performance (precision, in the sense as attached) from such circuits, at least at room temperature.  I used this circuit some years ago,



which grouped like 26-29mA between the half-dozen units I tested.

The load was a string of LEDs I think, drawn here for reference.  They might've had resistors, I forget.

This circuit has an overall Vbe tempco; using a current mirror topology with emitter degeneration (on both emitters) gets neutral tempco, but output current proportional to input.  Fine if you have a fixed supply somewhere, or can spare a zener (and have enough supply to make use of it; zeners under 5V have large tempco themselves) to make a local one.

Note the layout,



with the PTC fuse surrounded by copper pour from the pass device.  Since the fuse was routed to the connector on this, it didn't matter much, but when the output is from the collector alone, the fuse can be placed there (directly in series with C), and thermally connected even more directly, so that the PTC is heated up by collector dissipation.  In this way, a power limit up to 5W or so is feasible, without blowing up the transistor.  Maybe even 10 or 20W, with a bigger transistor (DPAK+), foldback current limiter topology (not just a CCS but it has some negative resistance), and the PTC embedded in the middle of it.

Power dissipation was excellent anyway with an inner plane (not shown), which also mostly negates the thermal coupling of this arrangement, but the thermal coupling is much better on 2-layer (but overall dissipation worse).

Tim

[mawyatt]

Think the Is(T) the OP was referring wrt the Ebers-Moll bipolar model is the saturation current of a PN junction, this is a totally different parameter than the bipolar transistor "Saturation" when the base-collector PN junction becomes forward biased with B-C, B-E and C-E current flowing.

Agree the Ebers-Moll model isn't a good model for the bipolar "Saturation" region, Gummel-Poon is better, VEBIC even better, and HICUM or Mextram even better yet. Some of the better bipolar models do a respectable job with the transistor "inverted"!!

Edit: Here's what we mean about "Inverted". This is a 2N3904 with the Curve Tracer setup so the zero volts and current are at the screen center. An AC waveform is applied across the Collector Emitter and the Base is Stepped with 2uA steps. The Vertical current scale factor is 1mA per div on the 1st image and 10uA per div on the second image, so 100X difference. The normal "Forward" mode is shown in the 1st image in the top right quadrant, and the "Reverse" or "Inverted" is shown in the second image in the lower left quadrant. The Horizontal voltage scale is same in both images at 0.5V per div. Note how the "Inverted" mode has much less gain (less current per step) and begins to enter breakdown around -2 volts Collector to Emitter.

Best,

[mawyatt]

Can't upload in the about thread???

Here's the second image!!