Integrated circuit parameters - Csub and Gsub ???

[Jolle]

I am doing a project where I have to know some of the properties in a process technology but I don't know where to find them so I hope some of you guys can help me.

I want to calculate the Q-factor of an inductor integrated in the top metal layer of a silicon chip by the dimensions (I use the paper "A physical model for planar spiral inductors on silicon" for the equations) and needs to know the following parameters:

l = overall length of spiral, w = line width, d = metal skin depth, t = metal thickness, N = number of turns, n = number of crossovers between spiral and center-tap = N - 1, tox M1-M2 = oxide thickness between spiral and centertap, tox = oxide thickness between spiral and substrate, Csub = substrate capacitance per unit area, Gsub = substrate conductance per unit area.

I have everything except for Csub and Gsub, which I don't know how to find and the paper states: "Csub and Gsub are the properties of the silicon substrate and are extracted from measured data". First of all I would like to know if anybody knows what they are for? The text says that it is "substrate capacitance per unit area" but capacitance in relation to what? And second if anybody knows where I might be able to find the values of these parameters that would be great? 

I have access to the process technology documentation that my design Is based on but I can't seem to find anything in them?! Are they maybe hidden somewhere as something else?

[T3sl4co1l]

Conductance depends on doping level; surely there is a bulk conductivity or surface equivalent in the data somewhere?

Perhaps you need to calculate the area equivalents, so that area conductance is determined by skin depth and area capacitance is determined by oxide thickness and k.

Tim

[Jolle]

Thanks for your reply  But I still can't find anything 

I have tried to search all my process documents for conductance/conductivity/bulk and all I find is some conductance values for different mosfet models. Maybe I am looking for something that isn't there but I was expecting a table showing different parameters for the different layers...

I have the following documents to the process technology:
CMOS process parameters
CMOS matching parameters
CMOS design rules
CMOS noise parameters
CMOS parasitic devices

From the name I would guess the information I am looking for is in the process parameter file, but is there another document that is more likely to the information I seek?

Sorry for my rookie questions, I am still relatively new to this integrated circuit world...

[T3sl4co1l]

Beats the hell out of me, I've never touched anything from a foundry before.  From what I know of semiconductors, I should expect such things are necessary and available, somewhere.

Is this school or work?  Surely there is an instructor or manager who can provide you with these answers.  With all the NDAs swarming about that crap, there's relatively little on the internet about it...

Tim

[free_electron]

Look for parameters called M1 M2 and M3 ( and so on ) they will give you the inter layer capacitance

[mattaw]

Normally there is a PDF manual that is really badly written. In there will be a table which should list the intra-layer capacitances per square (whatever a square is in your design kit - on one of mine it is 0.9nm to be difficult!).

If not perhaps you could simply do some squares of metal and then extract the parasitics through the EDA tools and guesstimate?

I am also interested in how many metal layers you have. If it is about 6-9 then the substrate is getting really far away now so the eqn. may be very inaccurate.

Just checking but are you sure there are not documented inductor PCells available in your PDK already that have much better models or best yet can be created at a specific value?

M