Multiple synchronized divide-by-n clocks

[zappedy]

What is a good circuit, or cheap IC, for generating div-by-10, div-by-12, and div-by-15, exactly synchronized so there are no unit delay differences? Starting with a 240MHz clock, and wanting 24, 20 and 16 MHz. All duty cycles must be 50% (45-55 is probably ok).

[RES]

Think you need to prescale the input frequency down first, and than divide further with  e.g a 74HC4040, because a 74VHC4040 max. frequency is 210MHz. A 74HC90 can divide by odd numbers to get to divide by 15.

[zappedy]

Thanks!

What about the synchronization? (Is it called edge synchronization?)

[Dave]

How exactly are you supposed to synchronize the edges if the clocks all have different frequencies?

[zappedy]

How exactly are you supposed to synchronize the edges if the clocks all have different frequencies?

The frequencies are "related", 16, 20 and 24 MHz divided from the same master clock. So every 10th clock on the 24Mhz, all three would "line up", unless there is differing unit delays involved.

The purpose of these clocks is to synchronize the logic analyzer with the device under inspection.

So I'm asking for a circuit which takes delays into account and produces several clocks that will line up.

[zappedy]

By the way, I'm only looking for a way get "synchronized" 16, 20 and 24MHz clocks with 50% duty cycles. If there is an easier or cheaper way than using a 240MHz master oscillator and dividers, I'm all ears!

I'm hoping to use a spare Raspberry Pi to generate the master clock, and capture the output of one device over USB at the same time. It does not seem to be possible to generate two or three different high frequency divide-by-n clocks using only settings on the RPi, because I think you are limited to grabbing the output from a PLL clock where you can set an integer and fractional divide, but only as one unit. Please correct me if I misunderstood this part.

[Andy Watson]

I would use a 4MHz clock and three PLLs to multiply up to 16, 20 and 24.

[zappedy]

I would use a 4MHz clock and three PLLs to multiply up to 16, 20 and 24.

But the PLLs are analog, how will the edges line up?

[Kilrah]

PLL stands for "Phase Locked Loop" - keeping phase in the desired relation is its very job.

[edavid]

Here's a simple clock generator board that you can buy:

http://www.ebay.com/itm/Adafruit-Si5351A-Clock-Generator-Breakout-Board-8KHz-to-160MHz-Arduino-3-3v-5v-/171909660637

[zappedy]

PLL stands for "Phase Locked Loop" - keeping phase in the desired relation is its very job.

Doh!

[C]

All duty cycles must be 50% (45-55 is probably ok).

To get this use the output of a FF and 2x input.
Ratio will be change output high specification vs change output low specification of FF.

wanting 24, 20 and 16 MHz.

So 48,40,32 as clocks.

exactly synchronized so there are no unit delay differences

To get synchronized, you need to know when to sync or reset all counters at same time.
In a digital system you are limited to add/remove 1/2 cycle of master clock as correction.

The purpose of these clocks is to synchronize the logic analyzer with the device under inspection.

You still need a phase lock to device under inspection.
You will need to phase lock to device clock or replace device clock.

[zappedy]

Adafruit Si5351A Clock Generator Breakout Board

Looks perfect! However, shipping to my country is $30, and then customs will be at least another $15, kind of steep for an $8 board...

I am still interested in a discrete design, but also anything you can do with the Raspberry Pi. Come to think of it, some of the Microchip PICs have multiple programmable PLLs. Got to go check my good-to-have drawer.

[edavid]

So find a similar board available in your own mysterious country