Just another constant current load stability question

[markus.p]

Hi, analog noob here.

I have designed and built a constant-current load for safely discharging supercapacitors.
After brute-force testing with different component values, the load operates perfectly in steady state, sinking a stable current that is linearly proportional to the DAC reference voltage setpoint.
However, when ramping down the setpoint, the current spikes and oscillates for a short period. Does anyone know why this happens and how I can fix it? The load will ONLY be used to draw fixed DC currents, never for pulsed or transient loads, so speed IS NOT important at all. Everything can be slow as long as it is stable.

Schematic:

The ACS37012 is a Hall effect current sensor outputting 1.65V + 0.044V/A.
The IXTH80N075L2 is an NMOS specifically designed for linear-mode operation, functioning as the load.

Ramp Up:

Green trace: Current I_DS measured with Keysight active current probe.
Blue trace: DAC voltage ramping up.
Yellow trace: Gate voltage.

The current ramps up slowly to ~2A and remains completely stable once it reaches its setpoint. Some brief transients can be observed.

Ramp Down:

The oscillating current spike (~10A) marked by the red arrow is my main concern. It appears to happen at the exact moment the DAC reference voltage begins to ramp down.

Ramp Down Zoomed:


What have I tested so far?
I have tested the following, without any observable difference in the current spike amplitude:

• Different values for C2, C3, C5, R2, and R4
• Faster and slower ramp times
• I_DS current setpoints
• +VCAP voltages

Any help is greatly appreciated

[Kleinstein]

A saftey discharge should be simple an reliable. The normal way is just a resistor at the capacitor. The next step up could be with an extra depletion mode MOSFET / relay that turns on one the supply is gone.

The capacitor C3 in the circuit cause extra issue - should change the value to 0.
It also helps to have real source resistance / shunt instead of the extra current sense chip.

[moffy]

You might want to consider a diode in series with Q1's drain, in case the polarity is reversed from expected.

[markus.p]

Thanks! Removing C3 does not change anything, unfortunately.
Yeah, I reckon the current sensor could be the culprit, but it would be cool to make it work with it

[markus.p]

Absolutely! I have implemented reverse polarity protection, just on another schematic sheet

[inse]

What would be the benefit of using the ACS current sensor above a shunt and the other half of the OPAMP?

[moffy]

The current spikes correspond to noise spikes on the DAC trace, the DAC trace should be completely noise free, is there some kind of grounding, ground noise issue?

[SiliconWizard]

I wouldn't have thought of using a Hall effect sensor as part of the current sink's feedback and I don't think I ever did that myself.
Could introduce too much phase lag, although that may not be the main culprit here. Just having a look at its datasheet.

[PCB.Wiz]

However, when ramping down the setpoint, the current spikes and oscillates for a short period.

That's all a bit strange. Normal ringing is a damped sine, whilst you have multiple spikes on both up and down.
The down has a wider pulse, but it suddenly ceases ringing, which is unusual.
Some ringing appears on the DAC in, so it's unclear if that is sourced or crosstalk. A source RC filter may help if this comes from the MCU.
Test again with a known clean DAC drive

C3 is a bit redundant, try it without that.  You could also scope pin7 of U2

[SiliconWizard]

Again never used a Hall effect sensor for this, but shouldn't be a big problem after all. You don't care about fast transients, your goal is to tame it as much as possible.

What's the capacitance of your load? You said supercap, a high-capacitance load like this will always make a current sink harder to tame.

C3 will indeed not make much difference given the already high gate capacitance of this MOSFET.

And yes, one can see current spikes about every 10 ms on any control voltage change, which stop when the control voltage becomes steady. In the decreasing case, instead of just very short current spikes, the first one triggers an oscillation which stops when a second spike occurs.

The noise on the DAC out just looks like coupled noise and it's perfectly normal. Just look at the current spikes, the scale is 5 A per div!! And you see pretty low coupled noise on Vdac. Nothing at all abnormal here.

But regarding the DAC out, if it's directly from a DAC out pin of a MCU, I wouldn't have loaded it with a 100 nF cap. Now if you have put a series resistor (that we don't see here)  that's a different thing.

[ve2ulu]

Inject small ac signal in the control loop to test the stability.
Low pass filter with high order between DAC and opamp.
Is possible you need complex feedback loop circuit to compensate the instability.

Always use the lower ampere mosfet possible in this type of circuit.
You dont need high power mosfet, gate have to much gain on impedance of the mosfet, use soft and weak mosfet,  is easy to drive.

Add small inductance on source of the mosfet add stability in current mode dc regulator, reduce ringing and oscillation, inductance cut the AC gain of the mosfet.
A resistor also work.
In some case, with high value inductor,  a resistor in parallel are good practice to limite the voltage spike in inductor and damp the circuit.
To test, inject small pulse in the control input and see on the scope the reaction, good control loop damp and smooth the curve.

[Terry Bites]

C3, R3 are adding an extra pole. Why put them there, brute force compensation?
I'd reduce the gain of the error amplifier with an R or series RC fom opamp output to inv input.
The ninv input doesnt need a such a large C if at all.
Deal with noise at source, right at the DAC if thats whre it comes from.
Always minimise current loop areas.

[MariuszD]

I estimate the loop crossover frequency at 1kHz. At this frequency, the Hall sensor with a bandwidth of 450kHz does not introduce a significant phase shift. The output of the amplifier with a resistance of 1.5kΩ, loaded with the capacitance Crss=4nF of the MOSFET (without C3), also does not introduce a significant phase shift at 1kHz. I suspect that the layout of the board is to blame and the oscillations are caused by the MOSFET itself.

Apply a 1ms rectangular pulse to the input and show us the oscilloscope trace; this will confirm whether the feedback loop is functioning correctly. Show the PCB layout.


The effect of C3 is harmful, so do all tests without it.

Show the oscillogram on which the oscillation frequency can be estimated, stretch the waveforms so that they are visible.

[Kleinstein]

The layout can be a big factor: Parasitic resistance and inductance can have quite some effect, as the signal from the current sensor is small. It corresponds to a small ( 44 mohms) resistor. It does not take much parasitic inductance to get a comparable impedance.

A resistor on the source side is not just for current measurement it also make the relation from control voltage (OP-amp output) to current more linear. With just the MOSFETs the gain is quite nonlinear and this can make the control slow at low current and fast (and prone to oscillation / ringing) at higher current.
Unless this is a very low voltage / high current (e.g. single solar cell) application there is no need to really avoid resistance at the source side and the power loss would not be that bad.

[Terry Bites]

Looking at what appears to be a 44mV/A sensor, it I'm not sure that it can provide enough feedback voltage.
Is the error amp struggling?

[temperance]

The oscillating current spike (~10A) marked by the red arrow is my main concern. It appears to happen at the exact moment the DAC reference voltage begins to ramp down.

What happens at the DAC output?

[MariuszD]

Looking at what appears to be a 44mV/A sensor, it I'm not sure that it can provide enough feedback voltage.
Is the error amp struggling?

This amplifier has an open-loop gain of 120dB. The MOSFET at 2A has a transconductance of 6 A/V, so the loop gain is barely 12dB lower than the op-amp itself.

I'm also wondering about the use of C2, I don't know which DAC was used, but the one shouldn't connect a capacitor to the output of a DAC that has an operational amplifier at the output.