Layout review: Inverting buck converter

[strobot]

Hi, I'm looking for feedback on the layout of a switching converter I'm working with.

It is a LMR14206 Buck converter configured to be an inverting buck/boost converter.  Red is the top layer, blue is the bottom layer ground pour.

[Bertho]

Both input and output capacitors are ceramic. With 9V over them, you will need at least a 50V ceramic capacitor to come anywhere near the 10uF and 47uF you have in the diagram (ceramic caps have a lower capacitance with a DC load because the C*V product is nearly constant). With the size on the board, you do not have this designed in. You may also need multiple ceramic caps in parallel.

The feedback trace takes input from under the diode. That means it will pick up all the switching noise on that trace. You are interested in having feedback on your output and that means that you need to have the feedback trace to come from the output capacitor.

If this is a 2-layer design, than you should consider to create a ground-plane and use that for all gnd connections.

[strobot]

Wow thanks for the feedback.  I was unaware that ceramics lost that much capacitance with DC bias.

This is the CV curve for the Murata GRM21BR61C106KE15L 10uF 16V cap I chose... wow


I will move the feedback trace to have it originate from the output cap. 

It will be a 2-layer design - the blue layer is the GND plane.  There is a cutout in the GND plane under the switching node.

[Bertho]

Wow thanks for the feedback.  I was unaware that ceramics lost that much capacitance with DC bias.

Yes, most people are unaware of that "feature".

It will be a 2-layer design - the blue layer is the GND plane.  There is a cutout in the GND plane under the switching node.

Then you should not make the cutout. It is not helping you in any useful or sensible way.

The ground-design should be altered and (nearly) all connections to GND should go through to the other side with vias. Your current design allows for loop-currents in the upper plane (i.e. you have ground-loops). You may want to use slightly smaller vias and then have more of them, placed on both sides of the high current path components. You need to analyze and act according to where the currents flow and which point is reference to what.

Do not connect vias on a T-pole, it works like an antenna. Use a thicker trace if the pass-through current is too high, but that is seldom a problem. For that matter, you can use much thicker traces all over for all high current paths. There is plenty of space.

[strobot]

Thanks again - here are my revisions.

[Bertho]

Thanks again - here are my revisions.

Good improvements. There are still a few things I'd like to comment on:
- The vias to the ground-plane should be on the other side of the pads. This is especially important for C2/C5 and C4/C6, which should be connected top side with the vias between the two caps (the short-side of the pad). Two vias should be enough.
- L1 should also be connected from the side(s) to the ground-plane (the short side of the pad). No need to make a small trace (or you create a bottleneck). The vias should be flooded in the copper on the top too (i.e. use a wide trace).

The two above suggestions reduce parasitic inductance of the traces and connections and therefore generate less EMI.

The input/output ground connections could suffice with one via on the short-side of the pads.

The connecting traces to the pads of U1 should be the same width as the pads. There is no reason to make a pinch in the connection. Also, the connections to pins 4 and 5 may be put closer to U1 and the connection to C3 may then be closed in a bit more. You could flood-fill pads for pins 4 and 5 completely.

[strobot]

Gotcha:
I'm going to leave U1 pin4 (SHDN) as a trace to be able to cut it and bodge wire to another control source if needed.

Thanks again for your help.

[Bertho]

I would lose the vias on the long-side of the pads.

[strobot]

OK, done.

Do you have any suggestions for filtering the switching regulator output?  Is adding an LC filter to the output sensible or would an LDO make more sense?

[Bertho]

OK, done.

Just one more thing I just saw. The gnd on J1 (input) should be connected directly to the capacitors. The input should hit C2/C5 directly. There is no good reason to loop that path.

Do you have any suggestions for filtering the switching regulator output?  Is adding an LC filter to the output sensible or would an LDO make more sense?

Well, I do not know what you used for calculating the output ripple or what you need the -9V for (haven't recalculated your values or analyzed the schematic as such). You can surely use either LC or LDO to filter more. Just remember that the feedback must stay exactly at the place where it is now.

The real question is what stability criteria you require at the output. From there more can be added.

[tszaboo]

I would add a reverse polarity protection on the input. With a MOSFET it doesnt drop that much voltage.
Like so:
http://nandblog.com/reverse-power-supply-connection-circuits/
 If you want to get rid of the noise, there are several ways to do this. First, you can add a ferrite bead on the output to get rid of the spikes, maybe with an other capacitor. Also, I suggest to put some different value ceramics on the output. A 10uF a 100nF and a 100pF has different ESR and ESL values at different frequencies. Also, you can add a bigger copper region on the output, that will form a very low inductance some picofarad capacitance on the output, good to reduce spikes. This is not that effective on the two layer boards, but it doesn't cost anything usually.
Adding an LDO is only sensible, if you have low frequency ripple on the output, as the PSRR of an LDO decreases with frequency.
Damn. I should write about this in more detail.

[Jay_Diddy_B]

Hi,
I believe the divider resistors are wrong.

The 1K Resistor should be on the bottom. The 10K7 resistor should be on the top.

What output current do you require?

Jay_Diddy_B

[strobot]

Hey Jay: you're right!  I caught this a couple posts ago and changed the schematic to reflect it but haven't posted the updated schematic.  If you look at the latest layout I posted, the resistors in the right place.  I'm actually planning on having the converter output about -4.5V as -9V is overkill for my needs.

NAND: This schematic is just a snapshot of part of a larger circuit.  There is definitely going to be reverse polarity protection on the battery input.  Thanks for your blog link!  I will definitely be browsing around there.

Bertho: made the change, thanks - definitely agree here.  I still need to make the ripple calculations with the new components.

The negative supply is going to power some opamps that will be used to amplify an electret microphone signal, and then eventually drive several pairs of headphones.  Ideally 200uV ripple would be a good target as that would make the supply about as quiet as a battery.

I need about the negative rail to be able to supply about 250mA.

[Bertho]

Ok, you need a very quiet psu...

I suggest you rotate the output capacitors 180 degrees and put the output-connector in-line with the output caps. Then you can connect the output connector without having to loop the gnd.

Before you hit the output connector J2, I's suggest to add a 100n and 470p..1n (C0G) in line with the output caps on the connector's side. The feedback takes from the center-point of the two output caps. J2 takes output from the smallest cap.

Further filtering may be required and a ferrite-bead after the 100n/1n combi followed again by a 100n/1n combi should get quite a bit of the HF noise removed. You then need to assure that you keep the rest of the power path away from the switcher so that it does not pick up noise again.
Depending your actual ripple, you need a real inductor to get that down. Make sure that the resonance of the LC filter is at >=10 times below the switching frequency. You should place the LC filter before the ferrite-bead filter.

[strobot]

I built up the board from the last revision of the layout.  The entire bottom layer is GND with 30 awg wire making the via connections to the bottom layer.  The extra, unpopulated footprints were for a potential additional LC filter at the output.


I used 1.02K for R1 and 10K for R2 because that is what I had on hand.  Everything else is accurate to the schematic. 

I'm getting an output of -8.216 V across a 144R load (random beefy resistor I had).  I really need to make an programmable load...

Scoped the output:


Thanks for the refinement suggestions, Bertho - I think I'm ready to commit this into the rest of the design with your filtering suggestions.

EDIT:  Ooops had the 20MHz BW limit button pushed.  The switching noise is actually worse:

[Niklas]

Is that noise measurement made with a probe that has the 10 cm ground clip cable attached? If so, remove it and replace with the clip on tip on the GND sleeve within millimeters from the probe's tip.

About a year ago I designed a low power PSU (5V at a few milliamps for sensors) with a Traco switcher as a pre-regulator followed by a LT3080 linear regulator to set the output voltage. The board had pi filters (C-L-C) both before and after the linear regulator. Ceramic capacitors (HF noise) in parallel with electrolytics (energy storage). The result was very low ripple on load step response and noise levels hardly distinguishable from the scope's noise. Replacing the ground lead on the probe with a shorter connection was vital.

This appnote gave me some hints back then
http://cds.linear.com/docs/en/application-note/an101f.pdf

[Bertho]

It works

Are you measuring real switch noise or is this (partly) induced in(to) the probes? That is always very hard to differentiate.
It looks like the coil is emptying itself and will therefore cause a resonant swing, which is very nasty to get rid of again due to the EMI properties. You want the PSU to have a consistent non-zero ripple current in the coil to avoid it from exhibiting resonant noise. That also requires a minimum load must be guaranteed. You can check the switch node with the scope to see what is happening.

I can see that you still looped the input connector's ground to the input capacitors. You should correct that small layout detail. I also suggest that you use physically larger input capacitors (with higher voltage rating), suggesting 1206, to have a better input filter on the line.

[strobot]

Niklas: I used the clip-on GND tip you're talking about.  It has a sheath that slips over the probe's ground sleeve and a pointy part sticking out parallel to the probe tip.  Great app note!  I'm going to read it in depth. 

Bertho: Thanks very much again - your advice has been invaluable.  I implemented your suggestions and flipped the input components as well.

[Bertho]

Bertho: Thanks very much again - your advice has been invaluable.  I implemented your suggestions and flipped the input components as well.

You are welcome.

The design look much more "clean" now, don't you think? That is a good sign

You should get rid of the GND via at J2 (output next to the text at the far left side)). That via is not helping because your reference should be from the output capacitor(s) and not the GND-plane at that stage.
Actually, the same argument I have for the GND via at J1 (at the far right side). And, you have the text at J1 reversed.

It looks like you have C2/C5 mounted on the side. If so, please don't do that as it increases parasitic inductance and therefore reduces the effect(iveness) of the capacitors.

[strobot]

OK - thanks I made the via changes.  Definitely looks more clean   I'm using the recommended footprint from the TDK datasheet.  I expanded the footprint to the max they recommend after hearing your comments.

[strobot]

EDIT: hahaaaaa so none of the scope pictures below are accurate as I reversed R1 and R2 when I placed them.  Its only outputting -0.8V.  Will repost new pics tomorrow.

I built up the latest layout:  I realized after I etched the board that I didn't have any 1206 caps, so I used a 1210 47uF and bodged a 0805 10uF in there.  There are 2 220pF on the output.


Output: look at that ripple reduction!


Switching node:

[senso]

As you guys are discussing switchers, would a ground-plane/pour in the top plane be worse than not having it?

[Bertho]

As you guys are discussing switchers, would a ground-plane/pour in the top plane be worse than not having it?

As a general rule, no its not bad but may not be good and can be worse. As much as it says it also says nothing... The point being, it depends on the hardware, goals and performance at many levels.

Primarily, you need to look at the currents. If you just pour copper on both sides and connect it at few to several places, then you may introduce ground-loop currents. These would show up as EMI emissions at best and instabilities at worst. You can do "stitching" with many vias to reduce the EMI (as seen in VHF/UHF designs), thereby reducing any potential differences, but if done without any thought, you may introduce odd EMI spikes at various frequencies.

Using a top-side pour is often not helping you very much because all components are already mounted on the top and will radiate regardless of the top-side ground-plane. The bottom ground-plane is specifically to manage DC currents effectively and act as a general shield for EMI emissions.

Making two separated shields (top and bottom pours) may give rise to one or more tuned antennas with the pours on each side acting as capacitor and the via interconnects as coils. The shielding effect of copper pours next to signal lines does not work as well in PSU designs because the traces are much wider and therefore "see" less of the neighbouring pour as small traces. Also, traces in copper pours act more like transmission lines than those outside the pour. Expressed transmission lines may be bad in high frequency switchers and can introduce additional poles in the regulation, causing instabilities.

Switchers at low frequencies (like a MC34063 10..100kHz) have fewer problems than high frequency (LTC* and the like at 500..2500kHz) switchers. Higher switch frequencies introduce more artifacts and are much more difficult to design with low EMI emissions. Lower frequency designs are (generally) much more forgiving.

My conclusion has always been to leave the top plane bare for PSUs, unless there is a very good reason to fill it.

[strobot]

OK, I fixed the feedback resistor orientation and was able to find a random chip inductor from an old PCB in the scrap heap.  I don't know its inductance. 

Updated schematic.  Input = 9 V; VO1, VO2 = -8.2V


I bodged the inductor to the output along with two 10uF ceramics.  I soldered in another 2 pin 0.100" pitch header across the 10uF output caps after I took the picture.  The output caps are indeed grounded - there is a small hole near the ends of the caps that connects via 30 awg wire to the bottom GND plane.


VIN


Switching node


VO1 (before LC filter)


VO2 (after LC filter)

[Bertho]

The output should be regulated at 8.95V, but you only get 8.2V. That means that the input voltage is too low or your divider is simply set optimistically high. If the controller is not in regulatory control, then measurements are not representative and the controller is working hard to get in the control region.

What diode are you using? The diode is an important component here and can generate a lot of loss. Also, what is the DCR of the switch coil (datasheet?)?

Your bootstrap capacitor is too small. The datasheet says it should be >=0.15uF, up to 1uF. You are on the low side with only 0.1uF. You should, at least for test purposes, stack another 0.1uF on top of the already mounted capacitor.

Where is that ~550kHz 10mV sine-wave coming from? It persists from input to output. Is that your feed supply?

What is the load? What happens with different loads attached?

Can you put two traces on the scope-image so the switch-timing can be correlated with the noise and flanks.