Logic circuit problem

[22]

Hi. I was working on circuit that set SR latch after rising edge of clock signal. It is shown on picture below but I don't know how to calculate the odd number of NAND gates needed in the delay circuit (?) to ensure stable change in SR latch. The pulse driving the S input is needed to be as short as possible but also long enough to ensure stable change in SR latch. The NAND gates are all the same SN74HC00D.

[donmr]

You need enough delay to ensure that the "Set" signal passes thru all of logic to the other input of the top NAND gate of the flop.

Among other things, your answer will depend on the loads on the Q and QN outputs.  You should probably put buffers on these to make the load a fixed value you can calculate.  It also depends on the implementation (wire lengths, capacitance, voltage, temp, ......).

This is not a very good design style, there are edge triggered flip-flops for a reason.

[Zero999]

Why use extra gates, when a simple RC circuit will do? If this was on an FPGA then I'd understand, but this a circuit made with discrete logic ICs, so there's no need for the extra gates.

[22]

Since I need at least 5 logic gates (4 gates in one package). That give me 3 unused, so I was trying to use them as a delay circuit.