Long, slow project: Modular DSO (backplane)

[c4757p]

I start too many long projects that I don't finish. The back-burner is full, so I'm emptying it - all previous projects are cancelled regardless of state of completion. (though I suppose that's not to say they'll never be raised from the dead)

Therefore, I decided I needed something modular, where I could work on a small module at a time, gradually moving toward completion in a less slogging way. I figured that an old idea I've been mulling over would be a good candidate for such a modular format: a DSO!

Yes, I'm going to attempt to design and construct a full DSO. This will be a long project probably spanning many months to even a couple years, given that I have to intertwine it with school. I'm just starting now. I plan to share full schematics, PCB and code as I go, so if you want any design ideas, have at them.

Initial specs, though these are set more in sand than stone (and the modular format will allow any of them to be upgraded at any time):
- 100 MHz analog bandwidth, switchable analog LPF for 20 MHz bandwidth
- 200 MHz real time sampling rate; will investigate the possibility of equ-time to extend this
- full proper frontend (down to 1mV/div at full bandwidth and up to 10V/div, switchable termination, probe detect)
- two or four channels (depending on how many frontend and acquisition boards are populated)
- the usual math capabilities
- serial decode?
- advanced, programmable digital trigger?
- segmented memory?

I have nearly completed the design of the backplane PCB, which contains seven card-edge slots to hold all the various components (will be CPU, video, 1 or 2 dual-channel acquisition, 1 or 2 dual-channel frontend) and has a 60W power supply to supply whatever power requirements I end up needing.

The slots are PCIe connectors but do not use actual PCIe. However, I have generally followed the PCIe pinout, replacing SMBUS by I2C, JTAG by SPI, and eight differential serial lanes by an 8-bit parallel BLVDS bus to handle bulk data transfers.

These are in the Git repository, https://github.com/cpavlina/os



Click for full size

[void_error]

I start too many long projects that I don't finish.

Same here.

I like the idea of a modular design. Looking forward to this

[c4757p]

Couple other quick and random ideas. I have an old and fucked up DS1052E (determined BER quite some time ago) from which I could scavenge parts that I don't want to pay for (some of this shit's expensive, and it adds up fast!).

• It actually uses the same ADCs I was considering using, and it's got five dual ADCs in it, so I could yank them and run them staggered the way Rigol did for a higher sampling rate.
• No need for 1 GHz like they have, though I shouldn't rule it out; it would make the layout complicated as I can probably only afford to do a four-layer and each one is a separate 8-bit parallel interface.
• 400 MHz would be plenty, as it puts the 100 MHz analog bandwidth fully below Nyquist at real time and removes the need for equivalent time.
• Also, I might yank the Blackfin DSP that they're using as the main processor and use it as a dedicated "math processor" to run things like FFT. Maybe I'll never get around to writing code for it - who knows - but I'll put it on the CPU card anyway.
• Main processor in mine will be an ARM; I just ordered a Freescale i.MX233 board to play with and I intend to try running Linux on that. Yes, it's a "multimedia" processor, yes, those features will go unused, and yes, I have a reason for choosing it.
• Shoving the waveform to the display will likely be done by a dedicated FPGA, or at least dedicated hardware in the acquisition FPGA (depends on how much I can fit in!). This FPGA will process the samples into an analog-style display; this "intensity-graded" format will be used as the native format for storing waveforms as it provides a good way to accurately represent the total waveform data when jumping down to a lower sample rate to conserve memory in a long capture.
• Along those lines, changing the sample rate to conserve memory will be done only this way as postprocessing on the samples; the ADCs will always run at full speed. This should eliminate the potential for aliasing as the time/div is changed.
• Until I decide to pony up for the rather expensive parts to build another set of two channels (one more entire frontend board and one more entire acquisition board), I'll include two "digital" inputs on the acquisition board as well. These will be usable as external trigger ports, and also if I do serial decode, will be able to capture digital data.
• The enclosure will be that of an 852D+ soldering station that shit itself something awful, rotated 90° to present the more oscilloscope-shaped side. It's about the right height and width, and it's deeper to accommodate the cardedge-based architecture.

[c4757p]

I'll be writing most small updates here, though I will continue to post big news here.

[c4757p]

Backplane came on Friday.

- 12V supply was ringing too much under load. Solved this by adding a damper (6.8 ohms + 1 nF) to the switching junction and some ceramic caps to the output.
- 3V3 fundemental-frequency ripple is too high. Going to replace the output capacitor with a higher capacitance, lower ESR device (probably a few in parallel). Don't have any sufficient on hand, so it'll wait until the next time I order parts.
- Forgot to get the damned Zener diode for the standby power supply. That'll wait too. I could probably cobble something together from other diodes or a TL431+resistors, but I'd rather just wait for the real part.

[c4757p]

More pictures

[ConKbot]

Modular designs are great for dividing a project down into bite sized chunks AKA "Ehh I dont really feel like nailing down all the details now"!    Working on a low phase noise 10 MHz reference at work, with phase noise being the primary design aspect.  I could add GPS disciplining, and a battery backup, and more outputs.  But its a side project, not a whole lot of time to dedicate, and I'd rather have it sooner than later, so gonna plonk down a few expansion headers with all the potentially relevant signals, power, and extra IO from the processor board to worry about that later 

[c4757p]

Not quite complete...

[charlespax]

Wow, this is awesome. I'm looking forward to seeing your progress.

Have you considered using a miniITX or similar format? You'd be able to use standard enclosures.

[c4757p]

Thanks!

Nah, I already have an enclosure. Though, I'll have to keep that in mind for future projects.

[JJalling]

Any exciting progress on this project?

/Jonas

[marshallh]

Too busy trolling irc to get any work done 








 

[c4757p]

Any exciting progress on this project?

Nothing exciting, progress is moving about as slowly as I figured it would. Should have power supply PCBs in the mail in a couple days. I'll post an update soon-ish, I guess.

Too busy trolling irc to get any work done 

Pretty much.

[timofonic]

Any news?

I suppose you already looked at some reverse engineering and new designs using FPGA. There's Hantek plus others such as that firmware replacement for a crappy DSO.

[c4757p]

Hah, news? In five days? Nope, still waiting for the PCBs, they seem to have taken the long way around...

This is going to be a really slow project - it's an expensive one...

[timofonic]

I found many projects that are a bit similar, but not so modular:

http://opencores.org/project,modular_oscilloscope

http://mhz100q.sourceforge.net

Here someone complained about why not more DIY Digital Oscilloscopes:

http://forums.hackaday.com/viewtopic.php?f=2&t=3112&p=13794