Low Noise AC Coupled Diff Amp

[CurtisSeizert]

Per David Hess's suggestion about a year and a half ago, I decided to try a differential version of the low frequency LNA I made using paralleled JFE2140s. I attached the schematic of the input stage. The rest of the amplifier is more or less recycled from the previous version, which was nice because I did not need to layout the entire board again. The relay that shorts the inputs to the ICM node is for switching inputs and decreasing the settling time. The noise target is less ambitious than the single ended one - around 1 nV/sqrt Hz flat band. I think that stability and usability are more important than sub 1 nV/sqrt Hz noise for most of the applications I envision for this thing. Similarly, the 1 MHz bandwidth of the single ended version proved to be more trouble than it was worth, so this one will probably cover out to 20-100 kHz depending on stability.

The topology of the input stage is a long-tailed pair with resistive loads (gain ~ 20) feeding a FDA (ADA4945-1). The feedback is applied to the (degenerated) sources of the input JFETs. This first gain stage feeds a difference amplifier, and the single ended output is high pass filtered (not shown in the attached pdf). The OCM of the FDA is driven by the center tap of the two gain setting source degeneration resistors, which ensures the total current across the feedback resistors is approximately zero. This should minimize the extent to which the drain current of the input JFETs varies with the common mode voltage. The input common mode is set to ca. -1.8V with the values shown in the schematic. This should allow at least 2V p-p common mode swing before either the cascode transistors or the current sink are driven near saturation.

The input HP filter has a very low breakpoint of about 60 uHz. This serves to keep the noise of the large value resistors in this filter below the passband of the amplifier (>10 mHz). It also ensures that any mismatches in the filter components won't lead to meaningful differential phase shifts between the two inputs within the passband. The input caps are +/-10%, and the resistors are 1%, so the worst case common mode gain from the input filter is -57dB. With minimal effort matching (i.e., the first two capacitors I pulled out), the common mode gain should be around -80dB at 10 mHz. This will probably be the limiting factor in CMRR below 10 Hz, so I might try to match a bit better. I think this is a better solution than DC coupling + bias voltage (as used in some Tektronix probes) for low noise work. The symmetry of the input stage should allow very low common mode gain. With some reasonable mismatches in components, I saw better than -100 dB in simulations, which would mean a CMRR of >150 dB at low frequencies (differential gain is 54 dB). With the matching of the LT5401 and the CMRR of the OPA210, a CMRR in excess of 140 dB seems likely, except at the very low end of the spectrum as mentioned before.

Because of the lower gain of the input stage, the noise of the ADA4945-1 will probably contribute somewhat to the overall noise and raise the 1/f corner somewhat. I have had problems simulating it with the ADA4945 model in LTSpice, but from some back of the envelope math, I think a 1/f corner around 1-2 Hz is likely. Near the low end of the passband, the noise of the input HP filters will become dominant at about 18 nV/rt Hz.

I have finished the schematic and the layout, but I am still deciding on the input connectors. I was thinking LEMO 0S with a shielded twisted pair cable, but dual SMAs are another option. Any suggestions?

[coppercone2]

12uF 220M

that is some big boy parts

[moffy]

First off, thanks for sharing the schematic, I especially like the bootstrapping around the cascode transistors which will help nullify a lot of the input capacitance of the multiple parralleled JFETs. No, other comments at present apart from I look forward to seeing the results.

[moffy]

Page 5 of the datasheet: https://www.ti.com/lit/ds/symlink/jfe2140.pdf?ts=1742430425010&ref_url=https%253A%252F%252Fduckduckgo.com%252F
Lists the variation in Vgs @ 2mA it goes from: -1.1V to -0.5v, so I don't think you can just parallel a number of the JFETs and expect them to equally share the current.

[CurtisSeizert]

Page 5 of the datasheet: https://www.ti.com/lit/ds/symlink/jfe2140.pdf?ts=1742430425010&ref_url=https%253A%252F%252Fduckduckgo.com%252F
Lists the variation in Vgs @ 2mA it goes from: -1.1V to -0.5v, so I don't think you can just parallel a number of the JFETs and expect them to equally share the current.

In practice, they are much tighter than that. You can pretty much take parts off the same tape without checking the Vgs at a given current and be fine. At one point, I checked 50 of them, but I don't have the spreadsheet of the results on this computer. More recently, I checked eight that I took off the same tape without any selection and got a Vgs range of -0.719V to -0.710V at 1 mA. In that case I was checking to parallel four of them to cancel the offsets as much as possible. I am not too worried about that, and in any event I have a jig to check them quickly if need be.

[moffy]

That's a pretty tight matching as long as they are handpicked/matched that's fine.

[moffy]

Why are you using a darlington pair for the cascode transistors, especially since the MBT6429 has such a high minimum gain of 500 and they are in the same package so somewhat matched? The darlington will compromise the HF performance a bit.

[David Hess]

More commonly the input cascode relies on a PNP transistor connected below the emitter degeneration to the current source, Q10 as shown below from the LT1001, so a Darlington is not required.

Sometimes the cascode bias comes from a completely separate current source and a resistor or zener diode replaces the diodes.

[Kleinstein]

The version of the LT1001 with the extra PNP to buffer the bootstrapping signal makes absolute sense. This way less extra current flows to the critical source nodes and the diodes to create the drop could work with a bit higher current.

I think the discrete transistor part should have enough gain (like 20-100 x) so that the noise of the ADA4945 should be not that relevant.
Already the resistors R2,R3,R5 and R7 add comparable noise.
I would be more worries about the current source at the low side. If the balance is not perfect, a little of the noise there could still enter. The current circuit uses the supply voltage as reference, which may not be very low noise.

I don't see a need for the ADA4945 common mode signal to follow the input CM voltage. It should be better to have the normal ground there. I would at least allow for an option to choose.

[Gerhard_dk4xp]

yes, methinks the Darlington is playing with fire. The devil always
finds work for unused gain.

I also noticed that all circuits of the form: cs input stage, opt. cascode,
op amp, feedback to source tend to develop a negative real part of the
input impedance. That can be plotted in Spice as real part (input signal
voltage / input current.)  The negative real part is in series with a capacitance.
Add an inductive source and you've got an oscillator.
The op amp is slow, so the feedback to the source is late. Amplitude-wise
the sources follow the input voltage. The cascode if present features a
low impedance load, so the input FETs feel more like a follower and the
slow feedback looks like a capacitive load for the follower.  That is much
like the standard microwave VCO design.
I have seen this even in designs of the gods, like AOE3. The only op amp
that seemed to work was a 3 GHz CFB by TI. But it drowned the input signal
in its 1/f noise, even after 40 dB of preamplification by the FETs.

Watch the 180° phase shift of the input impedance between 100 KHz and
50 MHz. (yellow trace).
The 0.5% of the source resistors won't help much. The source impedance is
in parallel to them and that depends on the DC bias current.
 

[CurtisSeizert]

Why are you using a darlington pair for the cascode transistors, especially since the MBT6429 has such a high minimum gain of 500 and they are in the same package so somewhat matched? The darlington will compromise the HF performance a bit.

The current noise of the cascode becomes problematic at low frequencies. The resulting voltage noise e_n = i_n(cascode) * (1/g_m + Rs) is no issue for wideband noise, but the 1/f corner for the MMBT6429 is pretty high, about 5 kHz. If you extrapolate from the datasheet graph for a 3 mA collector current you get about 700 pA/sqrt Hz at 10 mHz, so with the actual collector current of about 5.5 mA, you would get around 1 nA/sqrt Hz. This would give a total RTI noise of voltage of about 35 nv/sqrt Hz. The situation would be somewhat improved with a larger die transistor with a lower 1/f corner for current noise.

You can simulate this in spice, but BJT models don't tend to include the flicker noise coefficient (KF) parameter, which defaults to zero. None of the BJT models included in LTSpice have this parameter listed. I get a good match with the datasheet current noise plots with a KF = 1f for the MMBT6429 using the rest of Onsemi's spice model. I used the HN4C51J common base dual NPN BJT as the cascode in the single ended version and investigated its noise behavior as part of that. Interestingly, KF=0.0085f gave the best fit for my data with that one, and the noise figure  would be about 6 dB less than the extrapolated datasheet value at 0.1 Hz. In my simulations with the equivalent of 1 leg of the differential amplifier, the main noise source with a simple BJT cascode is by far the MMBT6429 current noise. With a >100x lower flicker noise coefficient, the HN4C51J (or its single version) would be about as good as the Darlington.

I did some simulations of the AC performance of the Darlington cascode vs one with the HN4C51J, and it seems that the simple BJT cascode with a lower flicker noise part may be the better option. The bandwidth limitation of these paralleled JFET frontends in my experience comes from the inductor-like output impedance of the source (often an op amp) and the input capacitance of the amplifier. With 8 fairly large geometry JFETs in parallel and a source with inductor-like output impedance, it becomes a struggle to maintain phase margin way before the cascode runs out of bandwidth. This is particularly true with a low noise amplifier that can't really take much source resistance to provide damping. That said, I will probably make the change and replace the Darlington, so thanks for making me think about this.

[Kleinstein]

The MBT6429 transistors have good performance at relatively low current, but seem to be not longer great at more than 1 mA. So I would really look for different transistors for the cascode. If nothing else helps, one could also split the cascode part over 2 or 3 transistors serving fewer JFETs.
There is anyway quite some thermal component from the transistors in the cascode, that could limit the CMRR.

[Gerhard_dk4xp]

You might consider the ROHM 2SD2704, probably the closest thing to
a super-Beta transistor that is still available.

<    https://www.digikey.de/de/products/detail/rohm-semiconductor/2SD2704KT146/1782307?s=N4IgTCBcDa4M4BMwHYAMAWEBdAvkA    >

The request for the spice model on digikey throws an error 404, therefore the attached
picture. It is Bob Widlar's JFET ersatz.  I have forgotten where the model comes from.
1/f is guessed by me.

[CurtisSeizert]

More commonly the input cascode relies on a PNP transistor connected below the emitter degeneration to the current source, Q10 as shown below from the LT1001, so a Darlington is not required.

Sometimes the cascode bias comes from a completely separate current source and a resistor or zener diode replaces the diodes.

The Darlington idea came from the input stage of the HP34420A. They even use the same BJTs. The reason I included it was current noise, but I have changed my mind on that because I can get the same performance by using a simple cascode with a different part.

The version of the LT1001 with the extra PNP to buffer the bootstrapping signal makes absolute sense. This way less extra current flows to the critical source nodes and the diodes to create the drop could work with a bit higher current.

The Darlington isn't really there to avoid needing to supply the base current of the cascode but to minimize 1/f current noise. With the relatively low impedance of the node to which the base is bootstrapped, I am not too concerned about a few tens of uA for biasing diodes. This doesn't really amount to much more than the net current flowing into those nodes arising from V_os of the OCM input for the FDA.

I don't see a need for the ADA4945 common mode signal to follow the input CM voltage. It should be better to have the normal ground there. I would at least allow for an option to choose.

This is actually an important part of the strategy for maximizing CMRR. With OCM grounded, the total current through the feedback resistors depends upon the common mode voltage of the inputs. This would essentially be the same as swapping the current sink of the diff pair with a resistive load. Add in some component mismatches, and the common mode gain increases from <-100 dB to ~-40dB.

I also noticed that all circuits of the form: cs input stage, opt. cascode,
op amp, feedback to source tend to develop a negative real part of the
input impedance. That can be plotted in Spice as real part (input signal
voltage / input current.)  The negative real part is in series with a capacitance.
Add an inductive source and you've got an oscillator.
The op amp is slow, so the feedback to the source is late. Amplitude-wise
the sources follow the input voltage. The cascode if present features a
low impedance load, so the input FETs feel more like a follower and the
slow feedback looks like a capacitive load for the follower.  That is much
like the standard microwave VCO design.
I have seen this even in designs of the gods, like AOE3. The only op amp
that seemed to work was a 3 GHz CFB by TI. But it drowned the input signal
in its 1/f noise, even after 40 dB of preamplification by the FETs.

Watch the 180° phase shift of the input impedance between 100 KHz and
50 MHz. (yellow trace).
The 0.5% of the source resistors won't help much. The source impedance is
in parallel to them and that depends on the DC bias current.
 

I have made a number of parallel JFET input stages, so I made sure to watch out for this when I was designing it. I ran stability analysis simulations with inductive inputs. I chose component values so that I would have at least 60 degrees of phase margin with 10uH at each input. The C || RC network at the inputs is there to help deal with inductive sources. Whether or not I populate the capacitor between the inputs will depend on how much capacitance to ground I see on the inputs of the unpopulated board.

[CurtisSeizert]

The MBT6429 transistors have good performance at relatively low current, but seem to be not longer great at more than 1 mA. So I would really look for different transistors for the cascode. If nothing else helps, one could also split the cascode part over 2 or 3 transistors serving fewer JFETs.
There is anyway quite some thermal component from the transistors in the cascode, that could limit the CMRR.

You might consider the ROHM 2SD2704, probably the closest thing to
a super-Beta transistor that is still available.

I will probably just go with the 2SC3324, which is the single of the HN4C51J or just parallel the devices in the latter depending on what I have on hand. I have used the dual in a very similar situation and have run tests on it so I know that the 1/f current noise will not be problematic in this application. I did at one point look at super beta transistors for this application, but in general they have terrible Early voltages, and I was not impressed with the 1/f noise in the parts I looked at. The VCE for the cascode transistors is small enough that thermal issues are not a huge concern. Even at these relatively high collector currents, the power dissipation should only be about 12 mW. Even with a SOT-23 thermal resistance of 500 C/W, that would only be about 6 C temperature rise.

[CurtisSeizert]

I got sidetracked with some other projects and had a fully assembled board for one of these sitting on the bench for a couple months. Other than missing a diode connection on a current mirror transistor, everything worked more or less as planned. CMRR is pretty good at ca. 125 dB between 1 Hz and 1 kHz (the attached Bode plot shows the CM gain with the differential gain set at 79 dB). The input caps are 12 uF +/-10% PP, but the ones I tested ended up all being within 1% of each other. The ones I chose were <0.5% mismatch. I tried trimming the capacitance of the input RC snubbers (which are after the AC coupling caps), but that only made things worse. Any surgeries on this are pretty tedious because of the 250M resistors to the CM voltage (about -1.8 V), so half measures during cleaning do not work out. The parasitic capacitance to ground of the two nets attached to the gates of the input JFETs are mismatched by less than 0.1 pF (both about 21.2 pF).

 The bandwidth goes out to about 100 kHz, with user selectable 0.01 and 0.1 Hz high pass filters (1st order) and 10 Hz and 10 kHz low pass filters (4th order Butterworth). Flatband noise is around 1 nV/rtHz. Quiescent current draw for the instrument is about 30 mA, so battery life is >100 h. With the "settle" switch that grounds the outputs of the inter-stage AC coupling caps via MMBF4117 JFETs, it is possible to get valid readings after switching inputs within a minute, even for the 0.01 Hz setting.

The biggest issue has been low frequency noise, and the analysis I have done points to the ADA4945-1 as the source of this. The differential amplifier stage operates with a gain of about 22, so the FDA needs to be reasonably quiet to not have a major impact on the noise. The op amp inputs see a differential impedance of about 1.3 k Ohms, so the significant 1/f current noise of the amplifier ends up being problematic. The fact that there is a significant reduction in noise in low power mode vs. high performance mode (which has higher current noise) supports this. Doing some back of the envelope math with extrapolated datasheet numbers, at 0.1 Hz I would expect the amplifier to contribute about 18.5 nV/rtHz in high performance mode and 12.6 nV/rtHz in low power mode to the RTI noise of the hybrid amp (measured at 24 and 18 nV/rtHz, respectively).

The best FDA choice to address this issue would be the THP210, which has current noise about 90x less than the ADA4945-1 if the datasheet is to be believed. I will probably try to bodge one in to test this. If that works, I will fix the schematics and layout to use the THP210 and upload the project to Github.

[CurtisSeizert]

There were actually two culprits that were contributing significantly to the low frequency noise of the input stage. Swapping out the ADA4945-1 with a THP210 helped somewhat, but it was only about 10-15% better. The next suspect was the follower + level shift feeding the inputs of the FDA. The THP210 datasheet doesn't warn of issues from the ICM having a DC offset relative to the OCM voltage, so I shorted that whole section. Now the FDA is attached to the load resistors, about 2.5V lower than the rail, so well within the specified CM range of the THP210. This did the trick for LF noise and reduced the RTI noise at 0.1 Hz from about 18 to 3.5 nV/rtHz. This is more in line with my expectations from earlier projects using paralleled JFE2140s in hybrid amplifiers.

Unfortunately, the FDA replacement cost about 20 dB of CMRR. My assumption at this point is that it's at least partly a product of all the wires soldered to pins rather than the tidier and more symmetrical original configuration.

I will revise the schematics and take some longer captures to be able to get an FFT of the noise floor down to 10 mHz and post that later.