LTSpice loop gain stability analysis

[Aleks]

Hi all,

I'm in the process of designing a 13.8V power supply, capable of delivering around 20A of continuous current (HAM, yup). I want to build my design from the scratch up and in order to do that, I want to be able to do stability analysis in simulation. My question is regarding how to do that in LTSpice i.e. where (and how) will I need to brake the feedback loop and do AC analysis to get the loop gain of the control loop.

This is the schematic that I'm starting off with (this is far from the desired one, but I'm taking small steps. Ah yeah, and the output voltage Vo-Vreg isn't set to the desired value of 13.8V):



It's transient analysis (loading it with 50 OHMs) of the opamp output is this :



I know that it oscillates, that's not the particular issue. It's frequency of oscillation is around 4.15 kHz. At this step, I want to do stability analysis of the control loop, and plot the response of the loop gain - ?A in order to determine it's phase margin and gain margin. From theory I know that in order to plot the loop gain I need to brake the loop, insert a test signal to the amplifier and look at the ratio V(feedback)/V(test) while grounding the input to the system. This is my first dilemma - what do I consider the "Input to the system" in this circuit configuration ?

After seeing LT's tutorial on "Stability of Op Amp Circuits" ( http://www.linear.com/solutions/4449 ) I know that in order not to disturb the DC operating point of the circuit, I need to insert a AC voltage source with a value of 1 in the negative feedback path of the loop, and then do the AC analysis. I naively put an AC source in this location (not changing anything else) :



And this is the result of the bode plot of the ratio V(vfb)/V(test) that I got :



This result doesn't seem right to me. From the graph I get that the PHASE margin is -12 degrees and the GAIN margin is -55 dB which doesn't make sense.

What am I doing wrong while making this analysis in LTSpice ?

Regards !

[AlfBaz]

It would appear you have +ve and -ve opamp inputs wrong way around

[f5r5e5d]

the output stage inverts, for more fun both the op amp and the output are integrators, each adding 90 degrees phase shift

I recommend starting with a much simpler circuit

[Jay_Diddy_B]

Hi Aleks,

Can you attach your LTspice file to your post?

Regards,

Jay_Diddy_B

[Aleks]

It would appear you have +ve and -ve opamp inputs wrong way around

No I haven't, the output through Q5 (which is a emitter follower) is connected to the parallel combination of the 4 2N3055 which are connected in common emitter - so the signal is inverted by 180 degrees theoretically)

I recommend starting with a much simpler circuit

What will you recommend ? I don't want to go back to the circuits like the one in LT's tutorial, my point is to analyse this kind of a configuration - more complex.

Hi Aleks,

Can you attach your LTspice file to your post?

Regards,

Jay_Diddy_B

Sure. I've attached the simulation file and the spice model that I'm using for the TIP122.

Regards

[dom0]

Use an (NPN) emitter follower output stage. Seriously.

[Aleks]

Thanks for the input. I might switch to that along the way, but at this moment I'm interested _ONLY_ in making the loop analysis

[Alex Nikitin]

Thanks for the input. I might switch to that along the way, but at this moment I'm interested _ONLY_ in making the loop analysis

OK, try the following: break the NFB loop on AC by connecting a very large value capacitor (say, 100F) between Vfb and ground in your LTSpice circuit, and look at the Vreg output. This approach does not always give accurate results, however in your case you will see all you need to see  . The circuit can be easily compensated (if you prefer to stick to it) to be stable, but I'll leave it to you to find a way to do it  .

Cheers

Alex

[AlfBaz]

<noob alert>
since the circuit actually requires 180deg phase shift, no phase shift (0 deg) is bad, yes? Then the 12 degree phase margin you measured is 12 degrees in the wrong direction (below 0) doesn't it, in this case, need to be above zero? in other words you have a negative phase margin relative to 0 degrees?

If you place a 10nF cap across R8 the oscillation stops and the phase margin is above zero
</noob alert>

[Kleinstein]

There is a loop gain example that comes with LT spice. It's a little more complicated, but works well.

Regulation will need some more work. Keep in mind that the 1000µF at the output will have some ESR, this could ruin the stability of this simple circuit. Often it is useful to an output capacitor that is a combination of a small (e.g. 100 nF-1µF) low ESR cap and a larger one (e.g. 100 µF) with some ESR (0.1 Ohms range) or an extra series resistor.  Usually an integrating capacitor at the OP is also needed, unless a very slow ( << 1 MHz) OP is used.

[f5r5e5d]

the simple V probe is OK used in the right situation - where there's pretty much "one way information flow"

which is well approximated in circuits where the impedance difference is very large between the 2 sides of the probe - as in the feedback R and the op amp input - and of course this has to apply over the frequency range you want reasonable result


there is a problem in phase calculation and display in all software - it has to choose a reference "branch" for the phase plot - to start with there are infinite  n * 360 +/-180 degree choices

so you need to allow for using judgment on what the phase you're looking at in the plot has to do with the "definition" in a feedback formula


starting with a stable circuit in .TRAN gives a big leg up - you know the .AC phase/polarity differences with your probe and phase branch ambiguity can be mentally flipped around to agree with the .TRAN stable result
of course you may need to inject some actual transient energy as load or reference steps to see if the .Tran is really stable - as well as judge whether the max_time_step is small enough to show the fastest amplifying device  dynamics well enough in your sim

[crazy horse]

I would break it at the connection between Vreg and R8.

Insert your AC source from R8 to ground and set a DC offset in that AC source to correctly bias the circuit. This usually requires trial and error for correct DC offset down to a few decimal places, but only takes a few minutes.

Otherwise you could put a feed bridge in of a really big inductor between Vreg and R8, and a really big cap between AC source and R8.

[Jay_Diddy_B]

Hi Group,

I have had a look at this power supply. It has useful property that the collector of the NPN output transistors is ground. This allows the transistors to be bolted directly to the chassis.

I modified the LTspice model supplied by the original poster so I could measure the closed loop gain. Here is the modified model:



The positive rail, positive output, is really the small signal ground in this design. The reference voltage and the feedback are both connected to this rail.


The results show:




This is an undesirable double pole system, -40 dB/decade, and 180 degrees phase shift.

One of the poles comes from the op-amp. If you look at an op-amp Gain versus frequency:



The other pole comes from the output capacitor C1 and the load resistor R7, This is feed from the current source Q1-Q4 which is high impedance.

So the power supply has a desirable feature that the collectors of the transistors can be grounded, but it would be hard to come up with a satisfactory control loop.

Regards,

Jay_Diddy_B

[Pjotr]

..........................My question is regarding how to do that in LTSpice i.e. where (and how) will I need to brake the feedback loop and do AC analysis to get the loop gain of the control loop.

The standard trick how to this in PSpice is to break the loop with a large inductor. Then you inject an AC signal after the inductor through a large capacitor. Values for the inductor/capacitor can be  > 1K for good results. This keeps the loop closed for DC (operating point) but breaks the loop for AC. In your circuit you can break the loop this way at the output of the op-amp or any other low impedance point.