LTspice .tran issue —output node stuck flat

[Aelxis]

 Hi everyone,

I'm working on simulating a headphone amplifier circuit in LTspice and I've hit a wall. I'm trying to run a transient analysis (.tran 20m) and compare the input signal V(in) with the output signal at V(15). The input looks fine (a clean sine), but the output is always flat — just a straight line.

I’ve already checked a bunch of things:

transistor pin order (C B E) —looks correct,

potentiometer models and connections —I tried both subcircuits and splitting them into two resistors with a wiper node,

different biasing setups.
Still, the output node refuses to show any AC signal. I feel like I'm missing something obvious in the way the circuit is biased or how the pots are connected.
Has anyone run into this before, or can point me to what I should double‑check? Any hints would be really appreciated.
I'll attach the code and the schematic for you.

Thanks!
    UPDATE: I modified the schematic(under the name : circuit.PAC.modificat), I think it's bettter now, but the output signal is still flat when i try to compare (I'll attach the amplificator picture and link as well-https://web.archive.org/web/20061111170618/http://sound.westhost.com/project70.htm)

[Ian.M]

This appears to be a continuation of your previous topic: https://www.eevblog.com/forum/projects/ltspice-project/
As I mentioned there, you need to follow the Project 70 setup instructions to get the amplifier correctly biased.  If you don't the output rails and it doesn't amplify much if at all. 

In "Schematic3 initial.asc", your quiescent current (set by VR2) is too low, way out of spec, which means the upper output transistor Q3 is nearly cut off, and you are stepping VR1 through far to wide a range.  After coarse stepping like that to approximately find the desired 1/2 Vcc operating point, you need to refine the .step command to a much smaller range with more steps to narrow in on the operating point.



Also on a waveform with stepped DC bias, the autoranging makes it very hard to see small signals unless you select a single step in the waveform viewer.

"circuit.PAC.modificat.asc" is a mess.  You've got incorrect connections round the input, shorting the Zeners and the top end of RV1 to ground through the input source and also incorrect connections round VR2.   Hint: as VR2 is used as a variable resistor, with the wiper linked to one end of its track  not as a potentiometer you can omit VR2b completely from the schematic.

P.S. To avoid wasting everybody's time, please try to stick to ONE topic per project unless your new question does not in any way relate to the project description and progress so far.

[Aelxis]

I tried following your advice, but unfortunately it didn' t work for me. The output is still flat, even after adjusting VR1 and VR2. I’ll keep checking the biasing, but so far I haven’t managed to get the amplifier to behave as expected.

[Ian.M]

In "Schematic3 initial.asc" try .param VR1=0.619 VR2=0.897 (comment out the other .param and the .step), which got me very close to the desired 200mA quiescent current and 1/2 Vcc bias immediately before the output capacitor, and a gain of approx. 12.5 (22dB).

[Doctorandus_P]

P.S. To avoid wasting everybody's time, please try to stick to ONE topic per project unless your new question does not in any way relate to the project description and progress so far.

[mtwieg]

Yes, please stick to one topic.

I made some further modifications to make the schematic more consistent with the one on the webpage:
1. Fixed connection of V1 and input
2. Changed D1+D2 to a single 15V zener.
3. Changed supply voltage V2 to 20V
4. Fixed connection of the wiper of VR2

I found that the setting of VR2 to get ~200mA of quiescent current was extremely sensitive.  Needs to be between 0.93-0.95 to get useful bias current. Seems like the value of VR2 should be 10K or 5K, not 100K. Also, varying the supply voltage has a large impact on quiescent current, which seems bad.

After that, the output is biased to midsupply, and I see an AC gain of 22dB, consistent with what the webpage predicts. Distortion seems reasonable up to input levels of 300mV.

To be honest I don't entirely grasp the design of this circuit. The description on the webpage is hard to follow, lots of contradictions between the text and schematic. Hard to really tell if the circuit is working as intended.

[Aelxis]

It worked so much better now, thanks!