LTspice - unable to open library file

[Peabody]

I'm in the middle of my first LTspice experience, and a problem has me stumped.  I want to use the NDP6020P P-channel mosfet, and I've downloaded the Pspice library file for that part from the manufacturer.  But when I attempt to use it the way a half-dozen videos say I should, I get an error message saying "unable to open library file".  Then I tried letting LTspice create a subcircuit assembly for it, and then I get a little farther, but it errors out with:

u1:ed : Unknown circuit node "nc-01" requested in behavioral source

I can find no reference to nc-01 in any of the files.  So I don't know what this means.

Can anyone see anything wrong with the library file?  Does it work ok for you?
This is "NDP6020P.lib":

Code: [Select]

*FDS6575 at Temp. Electrical Model
*-------------------------------------
*$
.SUBCKT NDP6020P 20 10 30 50
*20=DRAIN 10=GATE 30=SOURCE 50=VTEMP
Rg 10 11x 1
Rdu 12x 1 1u
M1 2 1 4x 4x DMOS L=1u W=1u
.MODEL DMOS PMOS(VTO=-0.7 KP=1.9E+1
+THETA=0.25 VMAX=1.5E5 LEVEL=3)
Cgs 1 5x 1500p
Rd 20 4 4.1E-3
Dds 4 5x DDS
.MODEL DDS D(M=3.5E-1 VJ=8E-1 CJO=1200p)
Dbody 20 5x DBODY
.MODEL DBODY D(IS=9.3E-12 N=1 RS=5.2E-1 TT=25n)
Ra 4 2 4.1E-3
Rs 5x 5 0.5m
Ls 5 30 0.5n
M2 1 8 6 6 INTER
E2 8 6 4 1 2
.MODEL INTER PMOS(VTO=0 KP=10 LEVEL=1)
Cgdmax 7 4 2600p
Rcgd 7 4 10meg
Dgd 4 6 DGD
Rdgd 4 6 10meg
.MODEL DGD D(M=5.5E-1 VJ=4E-1 CJO=2600p)
M3 7 9 1 1 INTER
E3 9 1 4 1 -2
*ZX SECTION
EOUT 4x 6x poly(2) (1x,0) (3x,0) 0 0 0 0 1
FCOPY 0 3x VSENSE 1
RIN 1x 0 1G
VSENSE 6x 5x 0
RREF 3x 0 10m
*TEMP SECTION
ED 101 0 VALUE {V(50,100)}
VAMB 100 0 25
EKP 1x 0 101 0 .02
*VTO TEMP SECTION
EVTO 102 0 101 0 .0001
EVT 11x 12x 102 0 1
*DIODE THEMO BREAKDOWN SECTION
EBL VB1 VB2 101 0 .08
VBLK VB2 0 20
D DB1 20 DBLK
.MODEL DBLK D(IS=1E-14 CJO=.1p RS=.1)
EDB 0 DB1 VB1 0 1
.ENDS NDP6020P
*NDP6020P (Rev.A) 8/2/06 **ST

*$


[Quarlo Klobrigney]

Do you get this far?

[Jay_Diddy_B]

Hi,

I did a quick modification to the model I fixed the temperature so it would use the standard PMOS symbol which has 3 terminals.
The model listed needed a four terminal symbol.

I have place the model on the schematic. This is good practice because it makes the model transferable without knowledge of the file location.

Here is the model:



[ Specified attachment is not available ]


and result showing the gate plateau voltage.




I have attached the model.

Jay_Diddy_B

 PMOS model.asc (2.44 kB - downloaded 157 times.)

[Peabody]

Thanks very much, Jay_Diddy_B.  So there really was something wrong with the model, and it wasn't just me screwing something up.  I was wondering what that fourth terminal was all about.  Well I was able to get a different mosfet library file to work, so this one should now work for me.  I'm trying to simulate a solar-powered 1S lithium battery charger with load sharing, and having spent an entire day getting the solar panel simulated so it matches the specs of the panel, I thought the rest would be a breeze - until I ran into this library file.

Thanks again.  It turns out LTspice is very nifty.  I should have learned it long ago. And it turns out the typical load sharing circuit (P-channel mosfet, Schottky diode, and resistor) doesn't work so well with solar power.  Most of the time the battery is providing the power though the mosfet's body diode.  Not a good plan.  But I have a modification in mind.  :-)

[Jay_Diddy_B]

Hi Peabody and the group,

I am going to show another way to do this.

Step One - create a new LTspice symbol (.assy)

A new version of the PMOS symbol is required. It needs to have an additional pin. Pin 4 is junction temperature control.

From the File menu  click Open

Set the file type to .assy

Navigate the files on your PC till you find the LTspice .assy files.

In my case they are are at:

C:\Program Files\LTC\LTspiceXVII\lib\sym





Open the PMOS.assy symbol

Move the labels out of the way by dragging with the hand tool




From the Edit menu click Add Pin/Port




Label the new pin Tj

click OK

Place the pin on the symbol:




The pin should be placed on the grid.

In the File menu click Save As

Save the symbol in the project directory with the name PMOS_TJ:





To be continued ...

Jay_Diddy_B

[Jay_Diddy_B]

Hi,

Using the new LTspice symbol

Add the symbol to the schematic:

Click on the component icon.

using the arrow change the Top Directory to the project directory:




Place the symbol on the schematic.

CTRL RIGHT-CLICK on the symbol to open the attributes editor





change the Prefix from MP to X. This is done because the model is a subcircuit model.
change the value to the name of the model NDP6020P:





The value should be the same as the subcircuit name.

Cut and place the model on the schematic using the .ap (SPICE Directive Icon).
(No modifications are required).

The model should now work.





The .assy and .asc files have to be in the same directory.

I have zipped them together, attached.

Jay_Diddy_B

 eevblog pmos model.zip (1.65 kB - downloaded 122 times.)

[Peabody]

Thanks for all that work, but I don't understand how this is better than your first version.  The mosfet actually has three pins, not four.  It's just a TO-220.

[Zero999]

Thanks for all that work, but I don't understand how this is better than your first version.  The mosfet actually has three pins, not four.  It's just a TO-220.

You didn't read his post thoroughly. The fourth pin isn't a real pin. It tells the simulator the junction temperature of the part. Connect it to a voltage and it will interpret it as the temperature in °C.

[Jay_Diddy_B]

Hi,
as Zero999 said, the fourth pin was included by On-Semiconductor model the behavior of the MOSFET at different junction temperatures.

Here is a model that shows how RDSon changes with Tj:




And the results:




This corresponds to this on the datasheet:




Jay_Diddy_B

[Peabody]

I just wanted to thank everyone, particularly Jay_Diddy_B, and report that I was able to finish the simulation I was working on.  It was a circuit proposed by Andreas Spiess in a recent video to use the standard load sharing circuit used in USB-powered LIPO chargers in one that's powered by solar panels instead.  The answer is that the mosfet turns on only in total darkness, and at all other times the circuit behaves as a two-diode circuit, one diode being the body diode of the mosfet.  So the circuit really doesn't work well for solar.

[Peabody]

I have another problem involving the downloaded library file for an opamp version of my circuit.  It runs successfully using the LT1494 opamp, which is in the LTspice library.  But using the downloaded library of the MCP6041, a simple DC operating point simulation errors out with "iteration limit reached".  I've reproduced below the error log file and the successful log file, and the library file for the MCP6041.

Is there any way to fix this problem?

Code: [Select]

Error log file - bad run with MCP6041:

Circuit: * C:\Users\Owner\Documents\LTspiceXVII\OpAmp.asc

Instance "m:u1:14": Length shorter than recommended for a level 1 MOSFET.
Instance "m:u1:12": Length shorter than recommended for a level 1 MOSFET.
Instance "m:m1:1": Width narrower than recommended for a level 3 MOSFET.
Direct Newton iteration failed to find .op point.  (Use ".option noopiter" to skip.)
Starting Gmin stepping
Increasing initial diagonal Gmin to 100
Increasing initial diagonal Gmin to 1000
Gmin = 1000
Gmin = 107.374
Gmin = 11.5292
Gmin = 1.23794
vernier = 0.5
vernier = 0.25
vernier = 0.125
vernier = 0.0625
vernier = 0.03125
vernier = 0.015625
vernier = 0.0078125
vernier = 0.00390625
vernier = 0.00195313
Gmin = 1.23794
vernier = 0.000976563
vernier = 0.000488281
Gmin = 0
Gmin stepping failed

Starting source stepping with srcstepmethod=0
Source Step = 3.0303%
vernier = 0.25
Source Step = 0.0177557%
Starting source stepping with srcstepmethod=1
Source Step = 3.0303%
vernier = 0.25
Source stepping failed

Pseudo Transient failed in finding the operating point at 5 µs.
Fatal Error: Analysis Failed: Iteration limit reached


Code: [Select]

Good run with LT1494

Circuit: * C:\Users\Owner\Documents\LTspiceXVII\OpAmp.asc

Instance "m:m1:1": Width narrower than recommended for a level 3 MOSFET.
Direct Newton iteration failed to find .op point.  (Use ".option noopiter" to skip.)
Starting Gmin stepping
Gmin = 10
Gmin = 1.07374
Gmin = 0.115292
Gmin = 0.0123794
Gmin = 0.00132923
vernier = 0.5
vernier = 0.25
vernier = 0.125
vernier = 0.0625
Gmin = 0.00100083
vernier = 0.03125
vernier = 0.015625
vernier = 0.0078125
vernier = 0.00390625
vernier = 0.00195313
Gmin = 0.00100083
vernier = 0.000976563
vernier = 0.000488281
Gmin = 0
Gmin stepping succeeded in finding the operating point.


Code: [Select]

Library file for MCP6041:

.SUBCKT MCP6041 1 2 3 4 5
*               | | | | |
*               | | | | Output
*               | | | Negative Supply
*               | | Positive Supply
*               | Inverting Input
*               Non-inverting Input
*
********************************************************************************
* Software License Agreement                                                   *
*                                                                              *
* The software supplied herewith by Microchip Technology Incorporated (the     *
* 'Company') is intended and supplied to you, the Company's customer, for use  *
* soley and exclusively on Microchip products.                                 *
*                                                                              *
* The software is owned by the Company and/or its supplier, and is protected   *
* under applicable copyright laws. All rights are reserved. Any use in         *
* violation of the foregoing restrictions may subject the user to criminal     *
* sanctions under applicable laws, as well as to civil liability for the       *
* breach of the terms and conditions of this license.                          *
*                                                                              *
* THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES, WHETHER    *
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED        *
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO  *
* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR    *
* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.     *
********************************************************************************
*
* The following op-amps are covered by this model:
*      MCP6041,MCP6042,MCP6043,MCP6044
*
* Revision History:
*      REV A: 07-Sep-01, Created model
*      REV B: 27-Aug-06, Added over temperature, improved output stage,
*                        fixed overdrive recovery time
*      REV C: 09-Apr-07, Adjusted quiescent current to match spec
*      REV D: 27-Jul-07, Modified output impedance at expense of comparator operation
*                        to correct transient response with capacitive load
*
* Recommendations:
*      Use PSPICE (other simulators may require translation)
*      For a quick, effective design, use a combination of: data sheet
*            specs, bench testing, and simulations with this macromodel
*      For high impedance circuits, set GMIN=100F in the .OPTIONS statement
*
* Supported:
*      Typical performance for temperature range (-40 to 125) degrees Celsius
*      DC, AC, Transient, and Noise analyses.
*      Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,
*            open loop gain, voltage ranges, supply current, ... , etc.
*      Temperature effects for Ibias, Iquiescent, Iout short circuit
*            current, Vsat on both rails, Slew Rate vs. Temp and P.S.
*
* Not Supported:
*      Chip select (MCP6043)
*      Some Variation in specs vs. Power Supply Voltage
*      Monte Carlo (Vos, Ib), Process variation
*      Distortion (detailed non-linear behavior)
*      Behavior outside normal operating region
*
* Input Stage
V10  3 10 -500M
R10 10 11 69k
R11 10 12 69k
C12  1  0 6P
C11 11 12 95P
E12 71 14 POLY(6) 20 0 21 0 22 0 23 0 26 0 27 0 2.00M 10 10 29 29 1 1
G12 1 0 62 0 1m
M12 11 14 15 15 NMI
G13 1 2 62 0 20u
M14 12 2 15 15 NMI
G14 2 0 62 0 1m
C14  2  0 6P
I15 15 4 4U
V16 16 4 -300M
GD16 16 1 TABLE {V(16,1)} ((-100,-1p)(0,0)(1m,1u)(2m,1m))
V13 3 13 -300M
GD13 2 13 TABLE {V(2,13)} ((-100,-1p)(0,0)(1m,1u)(2m,1m))
R71  1  0 20.0E12
R72  2  0 20.0E12
R73  1  2 20.0E12
I80  1  2 500E-15
*
* Noise, PSRR, and CMRR
I20 21 20 423U
D20 20  0 DN1
D21  0 21 DN1
I22 22 23 1N
R22 22 0  1k
R23  0 23 1k
G26  0 26 POLY(2) 3 0 4 0   0.00 -79.4U -39.8U
R26 26  0 1
G27  0 27 POLY(2) 1 0 2 0 0 26u 26u
R27 27  0 1
*
* Open Loop Gain, Slew Rate
G30  0 30 12 11 3.2
R30 30  0 1.00K
I31 0 31 DC 338
R31 31  0 1 TC=2.25M,-15U
GD31 30 0 TABLE {V(30,31)} ((-100,-1n)(0,0)(1m,0.1)(2m,2))
I32 32 0 DC 535
R32 32  0 1 TC=2.02M,-11U
GD32 0 30 TABLE {V(30,32)} ((-2m,2)(-1m,0.1)(0,0)(100,-1n))
G33  0 33 30 0 1m
R33  33 0 3K
G34  0 34 33 0 1
R34  34 0 1K
C34  34 0 100M
G37  0 341 34 0 1m
R341  341 0 1k
C341  341 0 1.3N
G371  0 37 341 0 1m
R37  37 0 1K
C37  37 0 3N
G38  0 38 37 0 1m
R38  39 0 1K
L38  38 39 13M
E38  35 0 38 0 1
G35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(3.4k,1n))(3.5k,1))
G36 33 0 TABLE {V(35,4)} ((-3.5k,-1)((-3.4k,-1n)(0,0)(1,1n))
*
* Output Stage
R80 50 0 100MEG
G50 0 50 57 96 2
R58 57  96 0.50
R57 57  0 101k
C58  5  0 2.00P
G57  0 57 POLY(3) 3 0 4 0 35 0 0 10U 1.49U 9.1U
GD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
GD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
E55 55  0 POLY(2) 3 0 51 0 -0.7M 1 -40M
E56 56  0 POLY(2) 4 0 52 0 0.6M 1 -55M
R51 51 0 1k
R52 52 0 1k
GD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1))
GD52 50 52 TABLE {V(50,52)}  ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
G53  3  0 POLY(1) 51 0 -4U 1M
G54  0  4 POLY(1) 52 0 -4U -1M
*
* Current Limit
G99 96 5 99 0 1
R98 0 98 1 TC=-6.9M
G97 0 98 TABLE { V(96,5) } ((-11.0,-3.9M)(-1.00M,-3.87M)(0,0)(1.00M,3.23M)(11.0,3.26M))
E97 99 0 VALUE { V(98)*((V(3)-V(4))*1.39 + -1.5)}
D98 4 5 DESD
D99 5 3 DESD
*
* Temperature / Voltage Sensitive IQuiscent
R61 0 61 1 TC=2.52M,-4.31U
G61 3 4 61 0 1
G60 0 61 TABLE {V(3, 4)}
+ ((0,0)(700M,5.3N)(770M,10.0N)(1.00,480N)
+ (1.5,500N)(3.5,530N)(7.00,580N))
*
* Temperature Sensistive offset voltage
I73 0 70 DC 1uA
R74 0 70 1 TC=1.5
E75 1 71 70 0 1
*
* Temp Sensistive IBias
I62 0 62 DC 1uA
R62 0 62 REXP  210U
*
* Models
.MODEL NMI NMOS(L=2.00U W=42.0U KP=20.0U LEVEL=1 )
.MODEL DESD  D   N=1 IS=1.00E-15
.MODEL DN1 D   IS=1P KF=0.2F AF=1
.MODEL REXP RES TCE= 9
.ENDS MCP6041


[Ian.M]

If you want the LTspice gurus here to be keen to help you, you've gotta make it easy for them, so post your .asc file, zipped with the offending OPAMP library, and any other custom models and symbols you are using.   Meanwhile, if you also post an image of the schematic, us lesser mortals might spot something obvious!

[Peabody]

Ok, attached is a ZIP file containg the MCP6041 version of the .asc as well as the LT1494 version of the .asc, which is identical except for the opamp selection.  The LT version works fine, but the MCP version doesn't.  Also included are the library files for the opamp and mosfet, as well as the solar panel model I'm using.  So it's all the files needed to run the simulation.  I should note that the MCP6041 library also comes in a "COMP" version, which I've included in the ZIP, which supposedly is better suited when the part is used as a comparator. That version doesn't work either.

I'm also attaching a picture of the schematic.  It's pretty straightforward.  If the output voltage falls below the battery voltage, the opamp output goes low, which turns on the mosfet.  Otherwise the output is high and the mosfet is off.  Of course I could just select the LT part, but it costs $5, versus 60 cents for the MCP part.  The opamp just needs to work with inputs at or just above the upper rail so I don't have to use resistor dividers that sink current, and it has to have very low supply current.

Any solution for this problem would be appreciated.

[Jay_Diddy_B]

Hi Peabody and the group,

I was unable to open your zipfile on two computers.

What are you trying to achieve?

Model using an ideal diode



In this model I have implemented an ideal diode using the LTC4412.

The result show an output voltage that is 20mV less than the battery voltage, until the current from the solar panel is greater than the load current. At this point the output voltage is determined by the solar panel. Note that ideal diode controller, LTC4412, regulates the Vfwd at 20mV.

battery current = load current - solar panel current

I have attached the model.

Jay_Diddy_B

 4412 solar.asc (2.18 kB - downloaded 132 times.)

[Ian.M]

Peabody's SolarPanelVersion.zip is actually a 7-Zip archive (signature bytes:    37 7A BC AF 27 1C), not a real Zip file.   Either use 7-Zip to open it or rename it with extension .7z then IZarc will also open it.

If you try a .tran sim run, it says:

Code: [Select]

Time step too small; initial timepoint: trouble with node "u1:21"add the UIC option to skip finding the initial operating point, and you get:

Code: [Select]

Time step too small; initial timepoint: trouble with node "u1:30"which IMHO indicates something iffy about either the model's circuit topology or the components connected to those internal nodes.
Searching the model for components using node 21 (and the associated node 20) gives the lines:

Code: [Select]

E12 71 14 POLY(6) 20 0 21 0 22 0 23 0 26 0 27 0 2.00M 10 10 29 29 1 1
* Noise, PSRR, and CMRR
I20 21 20 423U
D20 20  0 DN1
D21  0 21 DN1
which is two diodes and a 423uA current source in a series loop, controlling a POLY^* voltage dependent voltage source. I've got no idea what its barfing on as DN1 diodes are simply:

Code: [Select]

.MODEL DN1 D   IS=1P KF=0.2F AF=1
Similarly for node 30:

Code: [Select]

G30  0 30 12 11 3.2
R30 30  0 1.00K
GD31 30 0 TABLE {V(30,31)} ((-100,-1n)(0,0)(1m,0.1)(2m,2))
GD32 0 30 TABLE {V(30,32)} ((-2m,2)(-1m,0.1)(0,0)(100,-1n))
G33  0 33 30 0 1m
which is a bunch of voltage dependent current sources(G30, GD31,GD32) in parallel driving a 1K load resistor.  Discontinuities in the first derivative due to the G TABLE sources *might* be the issue here.  It certainly doesn't help that GD31 and GD32 are driving one of the nodes controlling themselves!

* Legacy POLY controlled sources come from Berkeley SPICE 2G5 written in FORTRAN in 1981.  See Apendix B of its manual for usage details (page 38 onwards [here]).

[Peabody]

I'm sorry the Zip file was screwed up.  My 7zip was clearly set to create 7zip files, and I don't know how that happened.  Anyway, the correct Phil Katz Zip file is attached.

I'll also attach the simulation that results from the LT1494 .asc file, which runs fine.  It produces the same result as the one using an ideal diode posted by Jay_Diddy_B, but without the 20mV stepdown.  So I can just use that part.  But since this circuit might have some general use, I was really hoping to find an inexpensive part if possible.  I really suspect the MCP6041 will work fine, but I would feel better if the simulation confirmed that.

Ian.M, I appreciate your wading into the weeds of the library file.  I don't know what any of those definitions mean.  What I've found online is that Microchip's opamp spice models are written for Pspice, and lots of people have problems with them.  Is there any Pspice-to-LTspice translation algorithm, or is that not supposed to be needed?  Would my files run on Pspice if someone has that?

[Jay_Diddy_B]

Hi group,
Ian.M is right in that the Poly directive and Table directive can cause trouble.

OP-AMP MODELS

In general opamp models are based on the Boyle model:




The input stage is a transistor level model, but everything else is behavioural.
This model does not include noise simulation. Noise simulation and other features can be added.

In order to debug these you have to reconstruct the schematic from the netlist.

Here is an example of TL072:

(This is an eye chart and you probably can't read it).




The MCP6041 model is probably similar to this.



Back to OP's circuit

If I substitute an op-amp from the LTspice library, I selected the LTC6244HV, then it reveals a flaw in the functionality:





If the output of U1 is at ground, the P Channel MOSFET will fully turned on. If the voltage, V2, is higher than the battery voltage, current will flow D1 and M1 to the battery V1. The MOSFET does not turn-off. The circuit is not an ideal diode.

Because of this, there is no advantage to making the MCP6041 model work properly.

Jay_Diddy_B

[Ian.M]

Ian.M, I appreciate your wading into the weeds of the library file.  I don't know what any of those definitions mean.

The first letter of the component name (first item on a component's netlist line) specifies what type of component it is.  Then there's a list of nodes it connects to (number of nodes determined by the component) followed by any value,  parameters, etc. See LTspice® => Circuit Elements in the help file for the list of first letters, types and help for each.

What I've found online is that Microchip's opamp spice models are written for Pspice, and lots of people have problems with them.
...
Would my files run on Pspice if someone has that?

Microchip's models are often flaky.  Although they'll probably run better under the specific SPICE program they are written for, even that isn't certain if you try to do anything complex with them.

Is there any Pspice-to-LTspice translation algorithm, or is that not supposed to be needed?

If the manufacturer sticks to pure Berkeley SPICE 3 syntax, components, and restrictions on local topology, then translation should not be needed.  The problems start when they hack together models for a specific proprietary SPICE program and don't test them under other SPICEs.  Unfortunately A.D. (formerly L.T.)'s LTspice license restrictions on semiconductor manufacturers make it difficult for other manufacturers to test their models against LTspice. 

Its actually usually easier if a PSPICE flavor model bombs with netlist errors as that's usually due to it using proprietary extensions to specific components and one can look up the component in the PSPICE user guide and work out a SPICE 3 or LTspice equivalent line by line.  If OTOH it fails to converge, either establishing initial conditions or during a .tran run, or stalls, and the usual tweaks don't help, its a lot harder as you really need to grok the model to figure out what's actually broken.  Due to my limited skills I can't grok the whole circuit from a raw netlist so am forced to laboriously reverse engineer the model to a hierarchical subcircuit schematic that generates an exactly equivalent netlist, rearranging the schematic till it makes sense to me.  Then one usually will have to create a minimal test jig to test the subcircuit, and later, test the translated model recreated from the hierarchical subcircuit netlist.  It may still bomb when used in a more complex circuit . . .

[Peabody]

Back to OP's circuit

If I substitute an op-amp from the LTspice library, I selected the LTC6244HV, then it reveals a flaw in the functionality:

If the output of U1 is at ground, the P Channel MOSFET will fully turned on. If the voltage, V2, is higher than the battery voltage, current will flow D1 and M1 to the battery V1. The MOSFET does not turn-off. The circuit is not an ideal diode.

Because of this, there is no advantage to making the MCP6041 model work properly.

You've picked an opamp that doesn't work.  The LTC6244HV input common mode range only extends to 3.5V, whereas the LT1494 extends beyond the upper rail, as does the MCP6041.   If V2 is higher than the battery voltage, the output of U1 won't be low.  It will be high, and the mosfet will be off.  I don't see that there's any flaw.  And the simulation using the LT1494 that I posted in my previous post shows that it works perfectly.

[Peabody]

Ian.M, it seems I just need to go with the LT1494, and put a comment on the schematic that the MCP6041 will probably work too, but the Spice model doesn't work.

[Ian.M]

See LTspice component Opamps\UniversalOpamp2 (documented in examples\Educational\UniversalOpamp2.asc) which you can tweak to model a well-behaved 3rd party OPAMP.   N.B. it *WONT* model misbehavior outside a permitted common mode input range.

[Peabody]

I want it to balk if either input exceeds the common mode input range.  It's key to the design that the selected opamp's range should extend a little above the upper rail.  That allows it to work without needing any resistor dividers that just eat up current.

But I don't want to model opamp2 so it works in the circuit.  I already have the LT1494, which works perfectly, but is very expensive.  It would just be nice if I could successfully simulate the MCP6041, which is cheap.

By the way, apparently there is something called Pspice-for-TI, which TI makes available for free to its customers.  Since the Microchip models are supposedly written for Pspice, maybe their's would work on the TI app, assuming I could get it from them.  Anyway the pictures below are what I ended up with.  And the whole writeup is on my github repo:

https://github.com/gbhug5a/Solar-Power-Load-Sharing

[Ian.M]

Most OPAMP manufacturer's SPICE models are behavioral, not transistor level, so do not and cannot offer any insight into real-life behavior outside the recommended operating range for any datasheet parameter.  Even if their model has transistor level modelling of inputs and outputs, the behavioral block in the middle, and ideal bias current sources will still make its out of range characteristics untrustworthy.

Therefore there is absolutely no point in simulating with a specific OPAMP model that you are not going to buy and physically use, unless you have compared transistor level schematics and datasheet parameters of it and the one that you are going to use to assure yourself they are near-equivalent.

That's many times more work than configuring a generic model like UniversalOpamp2 correctly for the target OPAMP and also setting up conditional .measure statements to confirm that datasheet parameter limits of the target OPAMP will be respected. 

e.g.

Code: [Select]

.param CMRU=1.5 CMRL=1.0
.meas tran Check_PU when V(in+)=V(Vcc)-{CMRU}
.meas tran Check_PL when V(in+)=V(Vee)+{CMRL}
.meas tran Check_NU when V(in-)=V(Vcc)-{CMRU}
.meas tran Check_NL when V(in-)=V(Vee)+{CMRL}
the desired result being all the Check_XX measurements failing.  If any succeed you need to investigate the resulting time point closely.

[Peabody]

I understand it would be necessary to test whatever parts I select.  But it's of some comfort that the LT1494 in simulation switches exactly when it's supposed to switch, and behaves as I want at other points.  It would just be nice if I could say the same for the MCP6041.  Both opamps' common mode range extends beyond the rails, so in theory either should work.  In any case, I'll read up on the .meas stuff.