Making a PWM based voltage standard.

[MegaVolt]

Dithering is not a magic solution. If you get a normal PWM at 1 kHz and use 4 cycles to add 2 more bits, your frequency becomes 250 Hz. And accordingly the filter should get better. Otherwise you will see a wave with a dithering frequency on the output.

[MegaVolt]

The best magic is to stack two PWM channels with different gain. Or a combination of PWM+DAC. 

[Doctorandus_P]

I thank you very much for the documentation of the Valhalla, Adret & Fluke.
I've got some more reading to do And I also thank you in the name of the 20 or so other who had enough interest to download it.

@MIS42N
My main reason for adding two separate stages is to use higher PWM frequencies. I want to do automated measurements, and for this my goal is 4 or 5 digit settling times in 100ms. Not "just" DC. (I need to do some calculations to get this right)
But a bit stream repeating "twice a second" is not going to do it for me, and your filter is not going to attenuate the 2Hz ripple.

@kleinstein.
Calibrating the small part is not difficult (in theory). It just needs a "zero comparator" just like other standards comparisons. Then you use two resistors, and set the coarse PWM to one step below the resistor divider, and start adjusting with the small stepsto find zero. Then you set the coarse PWM one bit higher, and start adjusting with small steps in the other direction.

The only pre-condition ( <- My spelling correction wants to make a pee-condition out of this ) is that all the small steps combined must be bigger then a single big step.
You can repeat this at different voltages to measure differential non-linearity of the "big" steps. It's just software, so I may give this a try.
I intend to have a configurable overlap between the two (Jumpers or a single resistor replacement), so I can experiment with 12 to 16 bit PWM for the fist stage, which allows for higher base frequency and easier filtering or quicker settling times.
Using a ready made DAC, is extra hardware and you also have to combine it with the voltage reference. With PWM, you can combine them before (or halfway) the filter. And with 74HCT you can easily use 2 times 4 outputs (maybe 6 + 2 is better?) which again reduces costs.
Using a 10V reference does halve offset problems compared to 5V. But I'm not aiming for lab grade prescision here. 4 digits of real precision and 5 digits resolution is my minimum goal, while 5 digits of real precision with 6 digits resolution would be a plus, but that would be my upper limit.

My best meter is currently an 4000 count old Wavetek Meterman 35XP, and this PWM thing can easily outperform it in resolution.
It also has no serial output (it can be modified, it's on the chip)
The best meter I'm willing to put my money in would be a Brymen BM867s
It would be hard to beat for EUR150.
https://www.welectron.com/Brymen-BM867s-Multimeter_3
I just have to compare it with some other Brymens before I make a final decision.
It does need data logging though, so I can write a script and let it gather linearity data for a few hours.

I don't trust UNI-T because there is too much quality variance in their products.

[Kleinstein]

Using PWM also for the fine part is OK at the lower grade level. However it may introduce some INL if the PWM steps of the fine an coarse part coincide. So for a higher level (6 digits and more) it may be easier to use a DAC for the fine part instead of extra effort to really isolate the 2 PWM parts and do the tests to be sure.

One can use the extra modulation of the PWM setting also with a higher PWM frequency.  It is a way to reduce the ripple amplitude for the lowest frequency part. With the same overall resolution and the last 2 bits from modulation of the PMW setting the PWM frequencies goes up 4 times and only relatively low amplitide (e.g. 1/1000) is at the the original ripple frequency.  Keeping the PWM frequency the same and adding a little modulation for more resolution is usually also OK. There are lowere frequency components, but these come at a much lower amplitude. So the filter made for the main PWM frequency can usually also suppress these frequencies, at least to maybe 1/4 or 1/8 the main frequency.

For the measurement of the fine part it helps if the fine part covers 2 steps of the coarse part. For the simple test with a comparator one needs some of the fine part range ( nearly 1 step worst case) to get the first zero crossing and than an additional 1 step to get to the next.
With an auxiliary ADC to cover 1 coarse step one can get away with less range for the fine part.

A point easy overlooked is the buffer to drive the reference side of the switches. More switches in parallel add to the load to the buffer.
The fine part is way less critical and would not need much effort, but it may be a bad idea to use the same chip to switch both the coarse and fine part, as the fine part this way can effect the coase part quite a bit. 

[iMo]

.. At 40MHz the full pattern repeats in less than half a second, so if changes are made less frequently then the technique becomes applicable. In the particular application it is changed every few minutes. There is a project called picDIV which implies the PIC outputs have very little jitter, so it may be quite linear and accurate. ..

The low output jitter (for example as it is stated on the picdiv page - 2ps) applies only when the pic is driven from an outside source. I doubt one can get such a jitter while using a crystal, PLL, or RC with the onchip oscillator.

[MIS42N]

@MIS42N
My main reason for adding two separate stages is to use higher PWM frequencies. I want to do automated measurements, and for this my goal is 4 or 5 digit settling times in 100ms. Not "just" DC. (I need to do some calculations to get this right)
But a bit stream repeating "twice a second" is not going to do it for me, and your filter is not going to attenuate the 2Hz ripple.

I agree if you want 100ms settling times a 24 bit dither isn't going to do it for you. I could argue the case for a 16 bit output (10bits + 6 bit dither), that pattern repeats in just over a ms. But whatever floats your boat. I only mentioned the technique because I have used it extensively and it works for me. But that is application specific.

I must say, however, there is no 2Hz ripple as such. The output is a string of pulses that vary in width by 25ns (e.g. 500ns 500ns 525ns 500ns 500ns 525ns etc) and that is measurable at the first capacitor as a fluctuation of a couple of µV in a 300µV sawtooth. By the time it gets to the second cap, the sawtooth is in the µV region with the fluctuation down to nV. By the time the signal gets to the third cap the variation is lower than the step size (about 300nV) so of no consequence.

The low output jitter (for example as it is stated on the picdiv page - 2ps) applies only when the pic is driven from an outside source. I doubt one can get such a jitter while using a crystal, PLL, or RC with the onchip oscillator.

I use an OCXO as an external clock source.

[Kleinstein]

From my experience with the µC based ADC I can say that the µC can introduce some jitter and not so random phase variations. e.g. the clock to the UART or µC internal ADC can have a small, but still visible effect on the output timing.
This is likely not yet a problem at 20 bit resolution, but it can become an issue at 24 bit.
Similar a second PWM signal can interfere with the main signal, especially if with the same frequency. This would be in the µC, but also externally with the buffering of the reference and supply to the switches. If not careful this may even be a problem at the 16 boit level.

The bare crystal at the µC is more suceptable to interference (I saw up to some 10 ppm with the ADC) than an external oscillator. There is no need for an OCXO - a simple crystal should be good enough. However a mems or PLL based clock chip may show some jitter - likely still OK for some 20 Bits, but not ideal. Clock jitter and phase modulation gets more important with a higher PWM frequency, so there is also some advantage in a not so high clock frequency. Than even the cystal at the µC can be OK, with some care. With a lack of capability to measure the linearity one may still want to start on the safe side.

For good settling it helps to have a good filter - just 3 stages of RC is not very effective and gets a relatively slow settling with a given suppression of the ripple. With the relatively low frequencies an LC filter is no really practical - LC is practical for more than 1 MHz maybe 100 kHz.  An inductor may still help with the very high frequency content, that an active filter may not like very much.

[Doctorandus_P]

A quick look showed that small sized inductors are readily available upto about 100mH.

https://www.bourns.com/docs/Product-Datasheets/rlb.pdf
https://www.bourns.com/docs/Product-Datasheets/8250_series.pdf

Which translates to 628 Ohms @1kHz
2*pi*1000*100e-3 = 628.3185307179587

Which is indeed not much, but not negligible either, and indeed it probably helps with filtering out high frequency switching artifacts, but won't help with reducing ripple at low frequencies.

Maybe an inductor can reduce the effect of charge injection?

Non linearity is supposedly worst near the middle of the range.
I just had the idea of using two PWM outputs of the uC for the first stage. (They're cheap, most uC's have 10 or so of them)
Then output them at the same PWM frequency, but with 180 degree phase shift.
This adds symmetry in the buffer stage and also greatly reduces output ripple in the filter if the PWM outputs are joined after the first resistor.
Which means that for example if the outputs of the 74HCT541 have a 10k and 10k1 resistor, then directly after the resistors and 50% duty cycle it switches between approx 2.45V and 2.55V,

For duty cycles between 0% and 50% both the effective output frequency is doubled (easier filtering) and the output of the sum point switches between 0V and either 2.45V or 2.55V, depending which of the two phases is high.  For duty cycles >50% the switching will be between both outputs high, or one of them low.

So the total effect is that the PWM ripple is reduced with 75% by just adding one resistor (and a extra PWM channel and a few lines of firmware in the uC)

I'm not sure yet what sort of changes get introduced by switching currents in the power supply of the 74HCT. I guess that also would be difficult to simulate (I do not have much trust in simulation anyway) I was sort of hoping that constant PWM frequencies would result in a static error which is easy to calibrate out, but that may be wishful thinking.

Gosh, just realized:
When adding the signals with two resistors, and without any further filtering, the output will switch between 2.45V or 2.55V, and on top of that almost DC you see all introduced switching artifacts on your scope so that is a good way to compare performance of 74HCT540 versus 4053, and what some added inductors do.

[MegaVolt]

Which translates to 628 Ohms @1kHz
2*pi*1000*100e-3 = 628.3185307179587

It is worth considering the series resistance of this coil of 484 ohms. This can introduce a DC error by forming a divider or a voltage drop at a small current.

[ezalys]

What exactly does an ADI 20-bit DAC buy you over one of these PWM based DACs, besides: INL, offsets due to say, charge injection, resolution, bandwidth/settling time, bipolarity, and reduced nonlinearity around 0 volts and the reference voltage?

If I wanted a dead-stable voltage at coarse resolution with ok settling time, is this a reasonable route?

[iMo]

Which translates to 628 Ohms @1kHz
2*pi*1000*100e-3 = 628.3185307179587

It is worth considering the series resistance of this coil of 484 ohms. This can introduce a DC error by forming a divider or a voltage drop at a small current.

.. and TC=3930ppm/K for copper...

[Kleinstein]

What exactly does an ADI 20-bit DAC buy you over one of these PWM based DACs, besides: INL, offsets due to say, charge injection, resolution, bandwidth/settling time, bipolarity, and reduced nonlinearity around 0 volts and the reference voltage?

If I wanted a dead-stable voltage at coarse resolution with ok settling time, is this a reasonable route?

Compared to the ready made DACs the PWM solution can be quite stable in time and if made right very linear.

The down sides of the PWM solution is that it is slow and needs quite some effort for the circuit with a few point's that can get wrong.

Ready made DACs get quite expensive once you want INL in the single digit ppm range. However they get afforable in the 16 bit range and below. So for the lower resolution a PWM DAC is not really attractive anymore. It becomes attractive at more than 20 bits, if speed is not really needed.