FET is for startup, probably a few uA or something. Then the NPN (minus the diode-strapped NPN) sets normal operating bias. The top PNPs are a current mirror: consider what happens at nominal Vout, the PFET-NPN base is at Vout, so emitter is a diode less, then another diode less just because, then the 10k. The 10k sets quiescent current. (Probably the two Vbe's gives a desirable tempco that helps compensate things.)
The circled, erm rectangled, part, is characteristic. Notice the two bases at equal voltage, and the emitters at dissimilar loads: an extra some kohms in one leg. The two transistors likely have a large ratio of emitter areas, too. This is the basis of the bandgap reference.
Or, maybe the emitter ratios are in the current mirrors (the lower row of three PNPs, well four if you count the dual-collector as separate), that's fine too. Uh, I suppose they can't, not with that much emitter degeneration (if they're actually 2k, 2k and 1k as shown).
In any case, the ratios should be obvious since you're looking at chip layouts...I guess? Do...do you actually have a die shot of this part? Or did you mean just traditional (bipolar?) IC
schematics? 'Cuz there are a lot of things you'll be missing without that; IC designs are a bit richer than the schematic would suggest, and they never show dimensions (junction width/length/area) on these diagrams, which are often equivalent diagrams at that (this one, it seems, does show all its transistors, given the "contains" claim). There are indeed clever mysteries to uncover if you're puzzling over just the diagram...

Oh and the tapped resistor is probably laser or fuse trimmed. Yeah, it's... badly drawn. Or, weird that they show it at all really. Most times I think that would be drawn as fixed resistors, hiding the fact that it's trimmed. Anyway, give or take schematic errors (lack of junction dots, or a way to indicate that some of those connections may be cut), that would indeed be how it's laid out on chip, a bunch of resistors with metal links between them, connected to test pads to run a fusing current, or left out in space where a laser can blast 'em. I suppose the discrete option is more likely (pads for microprobing) since a laser process would most likely carve an 'L' track into a resistive patch and it would be silly to draw it this way.
Tim