FPGA should be straightforward, build the DSP equivalent of the analog circuit and you're set. Not many bits are needed, say 10 bits is enough for a lot of general control purposes; this affects the noise floor, which, should average out towards DC (behaving as a sigma-delta modulator, perhaps) and can be filtered for the noise mostly around Fsw and fractions thereof. Accumulators will need more bits of course, but also not too many as you likely won't have very long time constants. And waveforms can be generated with clock dividers in the usual way.
Continuous-time waveforms (or fractional-clock timings) might not be so easy to do, though some chips offer them, like, some MCUs have fractional-clock timing. Not sure how they implement that. If nothing else, it's a rare case that you need very precise PWM or frequency control: the driven network will rarely have much Q at all, so the frequency hardly needs to be very tightly controlled. This may be different for say wireless power application, where the Q factor can be quite high, and the adjustable range quite narrow. But there too, since the time constant is so long, another approximation method will do just fine, i.e. dithering / DDS. Which can produce spurious tones at subharmonic frequencies, but again, the network is itself a filter so you hardly mind (but this can be quite important for radio purposes).
Doing it with MCU, is entirely dependent on what peripherals they provide. A lot these days have event systems that can be routed internally, allowing complex logic with accurate timing even from simple e.g. PIC, AVR CPUs. And including current limit / fault trigger sorts of actions, directly in hardware. Not sure about the, say, ARM side of things, but probably triggered DMA serves as an even more advanced version, at minor expense to bus timing (since DMA might occasionally be delayed due to bus contention, but also, the bus is fast enough you might not care). Indeed, DMA has been demonstrated as Turing complete, on at least a PIC32 I think it was?
So as for DSP stuff, if you don't know about it at all, you have some reading to do, but basically you take the differential equations of the analog system, change dees to deltas and get the difference equations, then set the time difference (sample rate) small enough that the deltas still behave like dees. It's not quite this simple for higher-order networks*, but you're likely not using many of those in a control loop, so that's easy.
*A specific example: you want to reduce high-order filters to chains of 1-2 order filters, implemented usually with a "biquad" structure which is quite efficient in hardware or software, and is least sensitive to numerical stability issues. This mirrors the active analog case, where a high-order filter is built from chains of 2nd-order filters. In both cases, higher order per stage is possible, but the numeric stability / component tolerance gets very strict, very quickly as order goes up, so you don't gain much doing that.
Like uh, for point of reference, I once wrote a biquad filter on AVR, taking 195 cycles per stage (plus 30 overhead), 16-bit data size, 16 bit accumulators, signed fixed point arithmetic. At F_CPU = 32MHz, that's enough to run 6 or 7 filters cascaded on 22kHz mono audio, for example. Not bad for a piddy 8-bitter. An ARM will do that in a small fraction, and a DSP even tinier still; FPGA of course can churn out results synchronously, depending on how much hardware you want to commit / share / if pipelining is needed.
Tim
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