MPPT boost converter - board layout evaluation

[Miyuki]

Hi folks,
I finally finished board layout and routing I like and want to discuss it with more experienced if is here some obvious problems or it look ok
Im not sure about grounding I put in to ground mosfet heatsink, but I think it is good to ground it, but dont this make any problems ?

Single sided boadr with one link
Boost converter 100-150kHz
Controlled by MCU constant off time peak current mode
Input 30-150V up to 10A Output 170V

[capt bullshot]

No, it doesn't look good. My guess is it will fail on first power on.
Better concentrate all the power components including input and output capacitors to a as small as possible area. Input capacitor is missing anyway. Keep the traces (including GND) from the capacitors (you'll definitively have to add an input capacitor) to the MOSFET and catch diode as short as possible. Don't run them all around the PCB as you did. Try to make a GND plane.

This layout has quite large loop area for the switching nodes, these will cause all varieties of EMC related problems. Traces for the power traces could be wider, 10A will cause these in your layout to heat up.

[Kremmen]

Without going into details, your traces are far too long and winding. Also the placement of the main energy storing components (inductors and capacitors) should be carefully planned to minimize trace lengths to each other, the switches and the controller.
Do consider a two layer board with ground planes in strategic locations and to minimize trace inductances. See guidelines on proper design principles, they should be easy to find in the net. As is, the circuit will most likely radiate like hell and not work very well.

[thm_w]

Im not sure about grounding I put in to ground mosfet heatsink, but I think it is good to ground it, but dont this make any problems ?

If the FET has a metal tab, then thats not OK unless you put some insulating thermal pad behind it. If the FET is insulated plastic tab then you ground is good for the heatsink, performance will not be quite as good. You may want to consider a two layer board and a input fuse to make your life easier.

No, it doesn't look good. My guess is it will fail on first power on.
Better concentrate all the power components including input and output capacitors to a as small as possible area. Input capacitor is missing anyway. Keep the traces (including GND) from the capacitors (you'll definitively have to add an input capacitor) to the MOSFET and catch diode as short as possible. Don't run them all around the PCB as you did. Try to make a GND plane.

The input cap is on the bottom of the board.

[T3sl4co1l]

Fill the red layer with ground pour and stitch it to top side ground frequently.  Every ~2cm say, with priority around pins and multiple vias at high current connections.

Tim

[Miyuki]

It is not clearly visible I mark it wit input and output capacitors, output have big secondary capacitor near output
As I see it now Input loop can be little tighter, but now gate driver sit in it

[Miyuki]

Second attempt with much tighter current loop and one ground point
(voltage sense resistors not placed yet, but power stage is solid)

[In Vacuo Veritas]

10 amps? Think about it for a minute, then look at your *traces*. Also, be mindful that the input is often more demanding of proper decoupling than the output.
170v?? Clearance!

What about terminals? How you gonna toss 10A into that? Those terminals look flimsy for *one* amp!

[Siwastaja]

My tip for designing a switch mode converter:

Don't draw GND traces at all! It's either:
- A 100% complete, dedicated plane you connect through vias everywhere
- In a compromised situation: a combination of incomplete planes (automated pours from the CAD), which are stiched together with a lot of vias

For high-current DC things - in this case, input and output - follow the same practice.

With two layers only, it's:
1) A ground plane interrupted by only very short traces only when absolutely necessary
2) A large input voltage fill
3) A large output voltage fill
4) Only a relatively small area of other traces and component footprints interrupting numbers 2 and 3.

Try starting with the fills and leaving all the tracks out, first!

Tracks are only needed to signals such as feedback network, compensation network, enable input etc.

"Thick traces" are often an indication you are doing something wrong; you should be using large polygons and automated fills instead. While this is especially true for GND net, GND is not special; it's the same for Vin and Vout as well. Parasitic inductance is, after all, through the loop which includes power and ground equally; and power can equally shield things. Large power pours can also be used to conduct heat from the components.

Such a polygon- or plane-driven layout will look simpler and smaller than a track-based, as well. It can be even easier to draw.

Avoid single-layer designs. You are probably not trying to push the price of the PCB below $0.05 in quantities of millions, in which case single layer is sometimes used.

[Miyuki]

I can agree with wider traces (maybe polygons) than 100mil I used but wont see any benefit of multilayer to make current loop any smaller as all power components are already next to each other and cannot be any closer and decrease loop area

[T3sl4co1l]

Ah good, so that'll be like 20-30nH switching loop inductance.  Which won't cause problems if switching isn't very fast.  Say, (30nH) * (10A) / (5V) = 60ns or slower.  Also that switching is slower than whatever the resonance is, due to MOSFET Coss.  If they are around 100pF at Vin, then 30nH and 400pF has a resonance of 46MHz, which is pretty high (~10ns rise time) but be careful as modern transistors are quite fast and can sing at frequencies much higher!

Tim

[Miyuki]

Voltage from dI/dt doesn look like a big issue even at higher speed like 15ns if I understand it right as enough voltage margin and in worst case are semiconductors avalanche rated
But what little confuse me is that resonance part and how it interact with switching time

[Siwastaja]

I wouldn't count on the FETs avalanching as a part of normal operation. You are quickly losing all margin for error. I like to keep the avalanching as an extra safety margin and try to verify the Vds(max) is never exceeded. Because it's not trivial to accurately analyze the energy they burn in avalanche and whether that limit is exceeded; it's easier to verify the Vds is not exceeded, with a simple voltage measurement.


But, it's not only about whether the FETs survive with their Vds(max) or not - there are other reasons as well.

The EMI generated in the resonance of unsnubbed, too-fast-switching inductive loop can distract the controller to malfunction - in worst case, so it blows the FETs - has happened to me. So it's not only about the voltage rating of the FETs. And EMI's not only about passing regulations - bad enough, and the device interferes with itself.

The issue is magnified by the lack of planes, which could offer some shielding, and prevent electromagnetic coupling of switching and control side by offering shortest paths to the switching AC return currents.

Planes and fills offer lower inductance even when the components are already packed as closely together as possible - you can think the fill as a set of parallel traces, and think what happens to the inductance with parallel inductors. A fill is great because it automatically (with any modern PCB tool, that is) maximizes the area; the electricity will find its way to automatically utilize that area the best. It doesn't have downsides, only benefits, when it comes to GND, Vin, Vout... OTOH, on the switch node net, a fill too large could be a capacitive transmitter and has to be avoided!

[Miyuki]

So here is variant with polygons at all power traces also possibility of placing switching node on second side and reducing loop area. Can I somehow calculate inductance of this loop now, when it was almost rectangle it was simple and result was about 30nH but what now ?
And was that 30nH really that problem or can be just "simple" snubbed ?

[T3sl4co1l]

Even better!

Why would you not simply pour the whole underside with GND?  You can't do any better without using both layers.

Tim

[Miyuki]

So just pour one side with GND and let it be this way ?

[Siwastaja]

Now bring the grounds of the SMD components to that layer using vias, near those SMD components, so that their ground currents don't need to take the long route (through the through hole part legs).

Additionally, add a few vias between the ground pour on the two layers wherever there isn't already a via closeby. Such a small board with naturally existing stiching (i.e., through hole component pads), so you won't need many if any. But vias come for free so no harm done adding a few.

[Miyuki]

vias come for free ...

Sadly I have no manufacturer here who can do boards with vias for reasonable price so for plated board I must wait 3 weeks if not want to pay like 50$ a piece