Need advice on PCB layout

[Stupid Bear]

I'm starting a new project and not sure about the best way to go about laying this out. I have done dozens of multilayer boards including BGAs but this one is quite large. The PI7C9X3G1224GP is 18x18 grid with 1mm pitch and .6mm ball diameter which isn't too bad but what concerns me is the decoupling capacitors. Diodes Inc doesnt actually say how many I will need nor do they provide a suggested layout for where to place them. I also have never worked with blind or uvias before. All my previous BGAs were dogboned with thruhole vias and were generally under 150 pins or so. I am not sure where to start here. How many capacitors will i need and what is the best way to lay them out under the IC. Would I need to use via-in-pad and can I get away without having to do blind vias. It's really the vias that are giving me anxiety because I'm afraid that I will botch that up and have no way of knowing if there is a problem with it once I build and start debugging it. I included a diagram of the pinout. Looking for any advice on this. Thank you.

[negativ3]

I would first ask your chosen PCB manufacturer what they support for...

BGA pad diameter
minimum drill
finished via diameter
annular ring
minimum track/space
via-to-pad clearance

As a starting point get your design rules nailed down.

[Stupid Bear]

So I use several different companies. PCBway and JLCpcb for cheap and quick and then for more advanced things we have another list that includes Megacircuit, TTM and a couple others. I can get the traces and holes sizes pretty small where I'm confident that they can build it. I've just never made uVias or via in pad and although I know they can do it (They have made other boards for us in the past) I don't know the caveats of designing them. I'm mostly concerned if I will be able to place the caps on the backside and still be able to use thruhole vias or if component placement will interfere and force me use uVias. Also not knowing how many caps I should use is a problem as well. I've done other chips like MCU and FPGA where the MFG either provided that information to me or I was able to work around that somehow. But here it looks like I need to use most of the pins and I can't break them out with jumping around to other layers and interfering with the caps.

[langwadt]

I think 1mm is big enough that jlcpcb 4 layer rules won't need via in pad

[Stupid Bear]

I could definitely dogbone it but that leaves less room on the top layer to break out. That is only reason I considered via in pad. I'm way more worried about what to do with the bottom layer.