Need some help with designing a latch

[Code39]

Yay, my first post/topic on the EEVblog forums

Im currently designing a circuit which will have a 74LS90 as a frequency divider which will in turn drive an audio circuit, never mind about that, got most of that working atm

What I've been scratching my head over for the last week is to design a latch that will give a high output for the duration of the pulse if a push-button is pressed at the same time, and keep the output high for the duration of the pulse. And then give a low output after the pulse has gone low and stay low until the push-botton has been released and pressed again.

Now, you might be asking me why I'm using a 74LS90 as a frequency divider, the answer to that is that I'm using multipile pulses and timing it via an AND-gate. And we are talking really low frequencies here.

Following is a really crude sequencial diagram, drawn in Paint.
Had nothing else handy on this computer, please have me excused.



I've been drawing and thinking, but have not yet come up with something satisfactory.
So if anyone have an idea, please speak up. I already have some AND-gates and inverters in the circuit to spare, but it would be possible to change these out for other gates. And as allways, I'm trying to keep the chipcount low

[kizzap]

I'd try use something like an AND gate and a flip flop:

+V on input A so that there are no false triggers from all inputs being Low

[Christe4nM]

First thing I'd do is create a truth table. As seen in your timing diagram it will not work when only the button governs the output state. Actually we need to know what the previous state of either the output or the button was.

So (clk implied):
Button Prev_out Out
   0           0            0
   1           0            1
   0           1            0
   1           1            0

What I see here is that you would need an EXOR of 'button' and 'prev_out' ANDed with button.

Now to get the previous output you'll need a flipflop, clocked in this case. Also, since the output should only be high for 1 clk cycle you need it put through a flipflop.

Unfortunately I'm doing this on my phone, so no picture possible, but here is what I think should work:

Button into the EXOR and the AND gates. AND output into a clocked D-flipflop. Output of that flipflop is OUT. This is so fed into a second clocked D-flipflop, which output is 'prev_out', and in turn fed into the same EXOR as Button.

I'll try to post a drawing tomorrow if desired.

[Christe4nM]

Sorry for a second post, but editing is a disaster on my phone.

I made a mistake and something can be simpler. Did anyone notice? First we need to take the previous state of the Button instead of the output. Otherwise the output is toggled as long as button is high. Apart from that the truth table stays the same.
(The output is only clocked high when the button changes from low to high.)

Also we can eliminate the EXOR by taking "NOT prev_button" and ANDing it with "button".

EDIT: Now the flow is as seen in the image below

NOTE: if for some reason the button goes high and is clocked into the first flipflop before the AND gate can go high. The output will not change. If this is the case try adding another clocked flipflop directly where "Button" enters the schematic. Now the button state is clocked as well and everything should work synchronous.

Please let me know if this worked.

[Code39]

Sorry for a second post, but editing is a disaster on my phone.

I made a mistake and something can be simpler. Did anyone notice? First we need to take the previous state of the Button instead of the output. Otherwise the output is toggled as long as button is high. Apart from that the truth table stays the same.
(The output is only clocked high when the button changes from low to high.)

Also we can eliminate the EXOR by taking "NOT prev_button" and ANDing it with "button".

EDIT: Now the flow is as seen in the image below

NOTE: if for some reason the button goes high and is clocked into the first flipflop before the AND gate can go high. The output will not change. If this is the case try adding another clocked flipflop directly where "Button" enters the schematic. Now the button state is clocked as well and everything should work synchronous.

Please let me know if this worked.

Yep, that design worked perfectly as you described it. Thanks.

Though, the high period of the output is twice as long as I wanted it to be, if you compare your's and my timing diagram. I will work on that to see if I can divide it again, maybe by using an AND-gate between the clock and the output, but if you have any suggestions please let me know

It's been a long time since I've worked with digital electronics, so just starting to work the logic back in

[Christe4nM]

  Good to hear it works.

As far as a shorter puls on OUT: an AND between CLK and OUT was my first though as well.