NMOS outputs should swing to 74HC input high threshold, the question is when?
NMOS has active pull-down but passive pull-up, that means that the edge will slow down as it nears the high threshold, the actual rate being determined by the load capacitance - particularly important if the Z80 is driving the capacitance of a bus and multiple devices. Using TTL or TTL threshold 74HCT gives a more predictable timing and frees up timing budget that might be needed elsewhere - not such a problem these days with faster memory and peripherals, compared to, say, the 450ns UVEPROMS and SRAMS in the old days, but still good practice.