Normal vs. Vertical Boost Converter Placement/Layout

[tinfever]

I'm working on a 18V to 75V 8A boost converter layout and I'm trying to decide on the best component placement to minimize switch node ringing and switching losses. This controller IC is only rated for up to 85V on the switch node so there is very little margin for ringing or overshoot.

I'm comparing between the LM5171 datasheet suggested lateral layout and a vertical layout suggested by EPC for use with GaN FETs (I'm not using GaN FETs but I figured if it's optimal for GaN it should be optimal for Si).

I think I can see how the vertical layout with the return path directly beneath (0.14mm below) on the second layer could be optimal, and how the loop area of the path with the high-side FETs, low-side FETs, and output caps would be very small. However, I'm struggling to picture the current paths and tell whether it's actually better. I'm also suspicious as to why this layout isn't widely suggested if it's actually optimal.

I've attached images of my part placement with my best guess as the current paths in both switch states. +VBUS is the input, going through a current shunt to the inductor. SW1 is the switch node. +75V is the output. The grey loop is the loop that everything I read says to minimize.

Any thoughts on these placement options? Is it actually optimal to minimize the switching loop area formed by the FETs and output caps, even though current never flows through that entire loop?

[Phoenix]

You're right in that the grey loop is the one that matters. The problem current is the part that transitions between the MOSFET and diode during switching events - the harder (more inductance) the path is between the two devices the more the voltage will spike during the commutation.

I suspect the recommended layouts are as shown because the difference is so very small that it really only matters for ridiculously fast GaN devices. There is of course other things to consider such as the gate drive path which is more critical for the GaN devices, hence the layout places the gates closer to the drive IC.

[tinfever]

You're right in that the grey loop is the one that matters. The problem current is the part that transitions between the MOSFET and diode during switching events - the harder (more inductance) the path is between the two devices the more the voltage will spike during the commutation.

I suspect the recommended layouts are as shown because the difference is so very small that it really only matters for ridiculously fast GaN devices. There is of course other things to consider such as the gate drive path which is more critical for the GaN devices, hence the layout places the gates closer to the drive IC.

Thank you. I'm confused about why the different return paths I'm picturing in the vertical layout aren't a problem. It feels like the real problem would be the portion of the yellow loop that is different from the blue loop, since that difference would the high di/dt path. Would the return path when the high-side FETs are on actually be closer to the grey loop than the yellow figure-eight I drew?

Also, does the gate drive path matter more for GaN because of the max gate voltage is so close to the nominal drive level so there is minimal margin for overshoot?

[Phoenix]

For the vertical GaN one the actual loop area created is still very small because the rest of the return path is on the next PCB layer down (see the side view image you posted), and once you add big return planes the inductance will be very low.

It's all about the inductive loop area.

The GaN gate drives need to low inductance as well to drive on fast enough and to hold the switch off against unwanted miller capacitance turn on. Voltage ring overshoot may also be a problem if the driver has low damping.