Open Drain RESET circuit for 68000.

[paulca]

I started with a basic RC RESET circuit.

Then I pondered... but it's an open drain with a pull up... and the inputs are not schmitts triggered.

For similar reasons I have a 74LVC07 hex open drain buffer on the board.  Its there to allow 3v3 side to safely interact with the 5V pulled up open drains.

Plugging my RC circuit into 2 channels of that buffer to pull RESET and HALT for me "with an edge", sounded great.  But now I'm not so sure as those buffers are not schmitt trigger either.

I'm going to breadboard the LVC07 to see how well it behaves with slow rising inputs.... and scar the datasheet for max rise times

In my Z80 build I just fed RESET direct from the RC circuit.  It never bothered it.  The 68k is a bit different though, with the open drain protocol.  Granted the RC circuit I believe was a 10k into a 10uF, so a node pulling that low will only be pulling against a 10k which is my standard pull up anyway.

Am I overthinking?

DRAFT! C22 should be at least 10u, possibly 22u or 47.  The "random" HALT an RESET (no prefix) are 3v3 side interfaces to those signals.  I will check but Im 90% sure the buffer is tolerant of up to 5.5V on its inputs regardless of Vcc.


EDIT:  The "10k standard pullup" is my CMOS default.  I may opt for 4k7 for the NMOS pull ups, they are only a few cm long trace wise, but the other option I have on this board is a "variable" input voltage on the bus transcivers.  I can lower their Vcc to match the CPU levels if I MUST.

[pqass]

The 68000 needs at least 100ms for reset (see last paragraph on page 87 here, screenshot attached).

The Alan Clements book 3rd Ed. (no longer free download from archive.org, hmm) uses a 555 for reset (see attached). 
For my 68k8, rather than the debounce NANDs, I've just put a momentary button across the timing cap (0.1uF on pin 2)

[fchk]

If you need further help:

In the 80's there was the NDR Klein Computer ("Klein" German for small and the Surname of the designer). This was a modular system with CPU boards for Z80, 68000 and 68020, ROM, RAM cards, disk controller, video, sound, cassette tape interface. Everything complete with instructions, schematics and layouts - but in German. Nowadays there are Ai and translations tools so this should not be that big of a problem anymore. But it may serve as a starting point as all of your problems have already been solved.

This is the link to the archive website: https://www.ndr-nkc.de/

[paulca]

I feel the fear here.  I feel it too.  It IS a period processor. It expects things. I get it.

Thats why the only circuit this CPU sees is the wrapper box I put it in.  Beyond this circuit it's CMOS or I f up.

All those CPU_  prefixes go to LVC transceivers.  Then... if my play works out... Im in pure LVCMOS 3v3.

NMOS quirky die at the interface, including here.  Thats the goal.

[Benta]

The original 68k designs had relatively complex reset circuits. Modern ICs make life simpler.
This is what I'd do:

[EE_Audio]

You need a comparator or schmitt trigger. I prefer comparators for this because I have control of the threshold voltage that way, giving more accurate timing.

[paulca]

This is what I'd do:

I like that.  The MAX803 part looks good.  The HALT/RESET IN might need some attention for 3v3 use, but that's just a pFET each.... or the LVC07 to convert it to push pull.

[Benta]

This is what I'd do:

I like that.  The MAX803 part looks good.  The HALT/RESET IN might need some attention for 3v3 use, but that's just a pFET each.... or the LVC07 to convert it to push pull.

Yeah, you can remove D3 and D4 and drive those inputs from open-drain/collector outputs.

[paulca]

This is what I'd do:

I like that.  The MAX803 part looks good.  The HALT/RESET IN might need some attention for 3v3 use, but that's just a pFET each.... or the LVC07 to convert it to push pull.

Yeah, you can remove D3 and D4 and drive those inputs from open-drain/collector outputs.

Of course the buffers are single direction, so I need to level shift the value back the other way ... as it turns out, I got lucky,  I have exactly 2 free "outbound" transciever ports spare.

The "cheese"... the 3v3 side has four signals.  HALT/RESET and HALT_ASSERT, RESET_ASSERT

[HwAoRrDk]

Yeah, you can remove D3 and D4 and drive those inputs from open-drain/collector outputs.

Aren't D1 and D2 also superfluous given that the MAX803 is also open-drain output?

Although I suppose you'd still need them if using a push-pull output MAX809.

One thing also to note about the MAX80x series (and their clones) is that the timeout period is highly variable - depends on things like VCC voltage, temperature, etc. It would be wise to ensure that the minimum reset timeout period (approx. 100ms) is adequate.

If you want a through-hole part (TO-92), check out the Microchip MCP120 or Onsemi MC34164-5.

[Benta]

Yeah, you can remove D3 and D4 and drive those inputs from open-drain/collector outputs.

Aren't D1 and D2 also superfluous given that the MAX803 is also open-drain output?

If you remove them, Halt and Reset will be shorted.
The minimum guaranteed reset timeout for MAX80x is 140 ms.

[paulca]

Yeah, you can remove D3 and D4 and drive those inputs from open-drain/collector outputs.

Aren't D1 and D2 also superfluous given that the MAX803 is also open-drain output?

If you remove them, Halt and Reset will be shorted.
The minimum guaranteed reset timeout for MAX80x is 140 ms.

The lure into that trap is real though.  Because "YOU" pull "BOTH" for RESETing the CPU, so it's easy to start thinking of them as the same signal.  However they are of course indenpendant and bidirectional, which is the whole "What wait?  Oh..." part.

[Benta]

Thinking a bit more about it, VDD still needs to be connected to +5 V, but you can likely get away with connecting R1 and R2 to +3.3 V, making the two outputs compatible with the rest of your circuit.

[paulca]

Thinking a bit more about it, VDD still needs to be connected to +5 V, but you can likely get away with connecting R1 and R2 to +3.3 V, making the two outputs compatible with the rest of your circuit.

Yea I got them pulled to 5V. 

The current board is sort of two and a half voltage rails.  5V, VDDA, VDDB.

It "should" work "fine"with VDDA running from 5V, but if I get into CMOS/NMOS/TTL miss-matches issues I have the option to drop VDDA to 3v3 and force the ViH lower on the LVCs.  I expect the 68k with 4k7 pulls to 5V will be fine.

Everything CPU, is 5V and pulled 5V.  VDDA only powers the CPU side of the transicevers.  The "VDDB" side is all 3v3.

The 3v3, sees 4 CMOS push pull signals.  Outbound RESET/HALT_ASSERT and inbound just HALT/RESET.

[Benta]

OK.
I had a picture of your 68000 running at +5 and everything else at +3.3, but it's apparently a bit more mixed.

[paulca]

Damn!  It grew teeth and bites.

While routing I noticed my "CTL_nOE" signal went nowhere except a pull up.  A board killing mistake!

But... it's almost chicken and the egg.  The CTL_nOE is the drive pin on the LVC245 buffers carrying both directions of control signals.  So with it held high, nothing flows in or out and the downstream board and the memory sees a dead floating control bus (pull ups do exist).

But where do I get this CTL_nOE from?  I went down a few rabbit holes like "RESET" or "Address Strobe", but those would then kill the entire control bus outside of a bus transaction and/or during a RESET instruction by the CPU.  The hardware downstream needing to see that RESET signal would have the buffer it sees it by go dark.

The little MAX803 for it's size is once again the solution.  Behind it's OR diodes, it still says "POWER_GOOD" even if the CPU pulls RESET low.  It satisfies the LCV16T245 datasheet requirement that drives are puled high/off until power stabilises.  But also keeps the CTL bus alive through resets and halts.  If I hit the reset button though, CTL bus (and everything else on the RESET net) resets.Which is what is required.

[paulca]

What it ended up looking like..... until the weekend when the real one arrives.

[Benta]

One comment: I spec'd Schottky diodes for my suggested circuit, I encourage you to follow that. I'm not sure sure 1N4148s will give a stable "low" in all conditions.

Cheers.