Schematics here -
http://cyberfish.wecheer.com/blog/wp-content/uploads/2010/06/scope.png
The problem with that front end is that there is that the input overload protection will blow very easily. Any overvoltage input is directly shorted by the diodes - bad news!
that can be quite complex! just make sure you got 1st class degree. dont fail just because u ar doing this too much.
Perhaps, with modifications, it could be used as a digitizer card for SDR (software defined radio, GNUradio in particular)? 100Msps is very fast for a continuous capture digitizer card. The analog requirements are much simpler - 50 ohm or 75 ohm input, perhaps only a 500mVpp to 5Vpp or so input amplitude range, and much less need for overload protection.
I have never heard of it, but that sounds very interesting.
I'm not sure what you meant by continuous capture. Does that mean streaming samples? That won't work unless we make it a PCI[-E] card or something, since USB 2.0 would limit the rate to about 40Msps, 1 channel. Also, if the smallest signal is 500mVpp, AC coupled (sounds like it to me), a lot of the circuitry can be taken out - the DAC for offset, and programmable gain amplifier. I suppose it can just be an ADC with an FPGA coordinating the acquisition, and whatever interface chip to connect it to the computer.
Is 8-bit enough for SDR? The SDR I'm designing will be 14-bit if I can figure out how to solder the QFN chip by hand.
What's interesting about it is that the decoder chip (Micron) appears to be a general purpose DSP or FPGA since there's 8MB of DRAM and 512k of Flash on the board.
That's interesting! I briefly looked in to using cheap TV tuner cards with composite input as a high speed ADC. It should be possible by fiddling with the Linux drivers, and inserting TV-esque signal pulses to fool the tuner chip (maybe!)
Is 8-bit enough for SDR? The SDR I'm designing will be 14-bit if I can figure out how to solder the QFN chip by hand.
Have you seen SparkFun's skillet reflow soldering tutorial?
- Check the ADC biasing scheme
- Consider driving the ADC differentially (via fully differential amplifier, something like TI THS4130) as this usually yields to best dynamic range
- PGA will need the ground thermal pad vias, they are missing? Also, traces under the PGA create risk of short circuit for same reason, solder mask is not reliable insulator!
- Fill the top side with copper too and place stitching vias between top and bottom grounds in something like 10x10 mm grid
- Remove the thermals on non-through-hole component vias, they just make the layout worse
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- Add more global decoupling capacitor everywhere on your VCC nets
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- Do not share ground vias, use one via per ground connection
- Power distribution net seems somewhat flimsy considering what you are trying to do here
- Or even better, consider seriously using multilayer PCB for mixed signal project like this, SI and analog noise issues can drive you crazy otherwise
- If you can't afford that, then use as thin PCB substrate as you possibly can, 0.8 mm thick or even less.
- Try to use more SMD components, especially in the input stage
Is there other advantages to SMD components beside board size? I used through hole components there because I thought I may have to change components there later (eg, using variable capacitor for better matching), and it's easier with through hole.
Quote- Check the ADC biasing scheme
- Consider driving the ADC differentially (via fully differential amplifier, something like TI THS4130) as this usually yields to best dynamic rangeDo you mean the way reference is generated? I am using the internally generated Vref (1.25V).
I just read up on differential amplifiers, and they do seem to be more suitable. For the THS4130, the datasheet says it has both differential input and output. Does that mean for the output, I can just tie the negative to ground, and positive to input of the PGA?
Quote- PGA will need the ground thermal pad vias, they are missing? Also, traces under the PGA create risk of short circuit for same reason, solder mask is not reliable insulator!Hmm I totally ignored the thermal pads. Will look into that. I am not sure if I can completely eliminate traces under the PGA, but I'll see what I can do. Maybe I can make sure there is only one voltage, and make the thermal pad float (the datasheet says it's electrically insulated).
The FPGA also has a similar problem, but I can't think of a way to do the power distribution without using the space under the FPGA (2 voltages with pins on all 4 sides). Maybe I can move them to the solder layer, but I'm not sure how much that will help (since the vias still need to be there). Or maybe I can just push them away from the center to clear the thermal pad area.
Quote- Power distribution net seems somewhat flimsy considering what you are trying to do hereCan you please elaborate on that?
Quote- Try to use more SMD components, especially in the input stageIs there other advantages to SMD components beside board size? I used through hole components there because I thought I may have to change components there later (eg, using variable capacitor for better matching), and it's easier with through hole.
Oh and this is the first project I'm using SMD components, too .
Thanks again for your time.
Will make changes and post updated board tonight.
I'm working on something broadly similar that may either help or hinder you - a four-channel SDR - and have used a differential amplifier. Note that I have no idea if this configuration will work and would greatly appreciate any input from Janne and the other forum gurus before I build it
No, I mean that ADC inputs should be at some common mode voltage. If I understood the PGA datasheet correctly, it does not provide any kind of biasing.
Imagine that you have let's say, 1 volt differential signal, and the ADC is powered from 3.3 volts. If the common mode voltage would be 0 volts, then your positive input to the ADC would be at +0.5 volts and negative input would be at -0.5 volts. Now since ADC supplies are at 0 and 3.3 volts, the input common mode range would be violated. But if you rise the common mode to 1.65 volts, then you would have positive input at 2.15 volts and negative input at 1.15 volts. That would be perfectly acceptable. The differential amplifier will make this biasing easy using the Vocm pin, which is just tied to desired common mode voltage.However, AD9283 seems to be a bit tricky in this respect, it wants to bias the inputs by itself. However, it is mentioned in the datasheet that optimum common mode voltage would be around 0.3x analog supply voltage, or 1 volt when using 3 volt analog supply voltage.
This is one of the reasons I recommended the multilayer board, with basic 4 layer board you can dedicate the 2nd layer to contiguous ground plane and 3rd layer to power plane, and still you have two good routing layers. I don't know if it is wise to leave the thermal pad unconnected, would the heat become an issue, at least with PGA?
I meant that the power distribution is build from relatively narrow traces, instead of the plane, see above.
Like already said, SMD components have less inductance, or generally smaller parasitics. Even among those, smaller components are usually better in that respect. BTW, I think that SMD capacitors and resistors are much easier to change using two soldering irons, than through-hole ones, especially on multilayer or even through-plated boards.