Patch ground plane with top layer bridge - is it a good idea?

[ddavidebor]

Hi guys,

I'm designing a instrument for semicondutor phisics and i've a very stupid question.

Attached is the power supply of the instrument.

As you can see there are two vertical "stitch" on the top (red) layer. i've used them to lower ground impedance, especially for the 7805.

I kept feeling like i'm a bad person. Is there any technical reason not to do it or do i need psychological support?   

[Yansi]

I think this shouldn't make any problems, but...

You should consider different PCB routing technique. On a double sided boards, it is good to leave any wiring in the top layer (considering singlesided load of SMD) and keep the most solid grounplane on the bottom layer. Try not to cut the bottom gndplane with long traces, only short jumps.

For example in your design, try to move the link between C8 and C2 to the top layer, same for the link between C1 to C31, etc...

Or just make another solid groundplane on the TOP layer and stitch them with vias together, don't leave floating unconnected pools.

But these are only general suggestions, not certainly universal for any circuit. As often said: "it depends..."

[Ian.M]

Also, try to avoid slots in the groundplane between the regulators and their local decoupling caps.   Bad layout with too much loop inductance, can occasionally turn a supposedly innocent linear regulator into a shortwave band power oscillator.

[ddavidebor]

A big thanks <3 was one of those time when you have the problems literally in front of your face and you can't see them 

[Yansi]

Now it looks nice and clean. But please check your isolation gaps. Seems too small. (not exactly an electrical problem here with few volts, but more as a technological aspect. It is always better to try design the board that less precision technology and effort is needed for manufacturing. Saves cost too!)

 Use please something like 16mil or more for this THT stuff.  (I mean the polygon-to-pad or polygon-trace or trace-pad separation gap. Dunno exactly whats the name of the parameter in Altium)

Also the horizontal trace above the linregs seems to be too close to the pads. Leave there bigger separation/isolation gap, like that 16mils suggested.

[T3sl4co1l]

While the routing can be improved (as mentioned ^^ ), there's nothing wrong with the method.  Indeed, you shouldn't stop there!  Keep going, pour the entire negative space on both layers!  Stitch liberally with vias, and you can get performance almost as good as a four layer board (with internal ground planes).

Use please something like 16mil or more for this THT stuff.  (I mean the polygon-to-pad or polygon-trace or trace-pad separation gap. Dunno exactly whats the name of the parameter in Altium)

Meh, I use 10/10 rules for default.  No problem whatsoever up to 70V (i.e., including common SELV circuits like this), and doable by basically any manufacturer (6 or 7 mils being the industry baseline spec).

Tim

[German_EE]

Add another vote for a solid groundplane on one side and copper pours with multiple vias occupying unused areas on the other. I would also put a 100n to ground as close as possible to the input and output pins of each regulator.

[ddavidebor]

While the routing can be improved (as mentioned ^^ ), there's nothing wrong with the method.  Indeed, you shouldn't stop there!  Keep going, pour the entire negative space on both layers!  Stitch liberally with vias, and you can get performance almost as good as a four layer board (with internal ground planes).

Use please something like 16mil or more for this THT stuff.  (I mean the polygon-to-pad or polygon-trace or trace-pad separation gap. Dunno exactly whats the name of the parameter in Altium)

Meh, I use 10/10 rules for default.  No problem whatsoever up to 70V (i.e., including common SELV circuits like this), and doable by basically any manufacturer (6 or 7 mils being the industry baseline spec).

Tim

I had not though of a second ground plane, good idea !

Now it looks nice and clean. But please check your isolation gaps. Seems too small. (not exactly an electrical problem here with few volts, but more as a technological aspect. It is always better to try design the board that less precision technology and effort is needed for manufacturing. Saves cost too!)

 Use please something like 16mil or more for this THT stuff.  (I mean the polygon-to-pad or polygon-trace or trace-pad separation gap. Dunno exactly whats the name of the parameter in Altium)

Also the horizontal trace above the linregs seems to be too close to the pads. Leave there bigger separation/isolation gap, like that 16mils suggested.

Yeah thanks i generally rule check insulation after manual routing 

[Pjotr]

While the routing can be improved (as mentioned ^^ ), there's nothing wrong with the method.  Indeed, you shouldn't stop there!  Keep going, pour the entire negative space on both layers!  Stitch liberally with vias, and you can get performance almost as good as a four layer board (with internal ground planes).

Yup, pouring the board with copper at both sides avoids also the risk the board will bend due to the difference in thermal expansion of copper and epoxy. Although that risk is lower with a simple 2-layer board than a >= 4-layer board.

[KL27x]

Meh, I use 10/10 rules for default.  No problem whatsoever up to 70V (i.e., including common SELV circuits like this), and doable by basically any manufacturer (6 or 7 mils being the industry baseline spec).

If you ever have your pcbs shipped in panels with the bad ones simply marked out, and if you have ever examined some of them, you might notice that in some cases even 10 mil separations can be bridged. Not that this is going to necessarily matter you to, at all.

[T3sl4co1l]

Yeah, from what I've seen, PCB printing errors are either small tolerance, or large blobs.  The printing itself is repeatable within a few mils (for the cheaper manufacturers), so by printing alone, 4 mil rules would be pushing it, but 6 or 7 mils is several sigma and pretty safe to do.  The blob defects aren't so easy to deal with, being up to 100 mil across, perhaps?  I think the cause is poor adhesion of film/resist/plating, so an area flakes off.  Not like a density/porosity/speckle thing.

So you could probably deal with flaking defects with *really* large design rules, like 100mil+, but that's terrifically impractical for almost everything else.

Tim

[Yansi]

I have suggested increasing the rules to 16/16 mils because of simple fact, that mostly all of my PCBs with loads of THT components were always home-etched. If the design is meant to be "opensource" available for other makers, should be designed with such care not to increase  manufacturing complexity unnecessarily.

Otherwise it doesn't matter. Almost any chinese prototyping fab can go down to 6/6 rules. (The only thing which sux with them is the 0.3mm mnimum drill. Sometimes I just need less because of some BGAs with stupidly dense balls)