PCB Layout for TPS54202 DC-DC Converter

[girishv]

[ Specified attachment is not available ]Hi,

I am designing a DC-DC converter, 24V input and 5V/2A output. I am using TI TPS54202 and using the schematic provided by TI Webench Power Designer.

Here is the initial layout.



I have deviated the layout guidelines provided in the datasheet for the switching network. Please suggest how I can make this better?

[tooki]

For starters you seem to have entirely missed a connection in the feedback (voltage setting) network. As laid out here, it won't work at all.

The input caps (C1, C2) should be as close to the chip as possible, ideally with their grounds directly tied to the GND pin of the IC. (This is why, in TI's reference designs, and Webench, the SW connection actually goes under the input cap.) So should the feedback network (R1, R2, C4). The output caps (C5-C7) should also be rotated 180 degrees so their grounds are facing towards the chip.

Study the PCB layout in Webench and the one in the eval module: https://www.ti.com/lit/ug/slvuap3a/slvuap3a.pdf as well as the layout guidance in the datasheet.

[girishv]

For starters you seem to have entirely missed a connection in the feedback (voltage setting) network. As laid out here, it won't work at all.

The input caps (C1, C2) should be as close to the chip as possible, ideally with their grounds directly tied to the GND pin of the IC. (This is why, in TI's reference designs, and Webench, the SW connection actually goes under the input cap.) So should the feedback network (R1, R2, C4). The output caps (C5-C7) should also be rotated 180 degrees so their grounds are facing towards the chip.

Study the PCB layout in Webench and the one in the eval module: https://www.ti.com/lit/ug/slvuap3a/slvuap3a.pdf as well as the layout guidance in the datasheet.

Thank you very much for the feedback. I should have enabled the rats nest and verified all the connections. Totally stupid of me!

Further, I will work on your suggestions and redo the layout and post here.

Thanks again.

[Harry_22]

Hi! Fully agree with Tooki. You have to make ripple current paths as short as possible.

Every current is a closed line. I draw two lines of ripple current. The first flows through the upper MOSFET the second through the lower.
Your goal is to make their PCB journey shorter.

I don’t understand why you installed the diode rectifier. If you supply AC voltage you need to install an electrolytic capacitor. The reason is the same to short the ripple current from AC.

[T3sl4co1l]

Hi! Fully agree with Tooki. You have to make ripple current paths as short as possible.

Every current is a closed line. I draw two lines of ripple current. The first flows through the upper MOSFET the second through the lower.

Note that the local switching loop is terminated by the bypass capacitor adjacent to the regulator.  The loop including the inductor is hardly relevant as dI/dt is small -- literally, the inductor breaks the high-frequency loop.  At the remaining (low) frequencies, the GND plane stitching and area are more than adequate for commercial EMC purposes, I would say.

There might still be feed-through due to EPR and EPC of the inductor (equivalent parallel..., in analogy to a capacitor's ESR/ESL), for which one will need the characteristics of the inductor to analyze.  It's almost certainly fine, short of an intentionally-pathological component.

The input ferrite bead might still conduct enough EMI off the input cap to be a problem, though.

Tim

[girishv]

Hi! Fully agree with Tooki. You have to make ripple current paths as short as possible.

Every current is a closed line. I draw two lines of ripple current. The first flows through the upper MOSFET the second through the lower.
Your goal is to make their PCB journey shorter.

I am redoing the layout based on suggestions received by @Tooki and yourself. I will try to keep PCB traces smaller and wider as suggested.

I don’t understand why you installed the diode rectifier. If you supply AC voltage you need to install an electrolytic capacitor. The reason is the same to short the ripple current from AC.

The input will come from an external DC source. There is an outside chance, where the input lines will be swapped. I could have used a P-Channel Mosfet for reverse polarity protection. Since, I had a luxury of 24V input, I used a bridge.

[girishv]

Please ignore this post. I am revising the feedback circuit layout.

Here is the revised layout.



I tried to worked on suggestions by @Tooki and @Harry_22 to keep the switching current traces short. I am not sure about layout of output capacitors. Please suggest.

@T3sl4co1l I can remove the ferrite bead if needed.

[daisizhou]

Please watch the video below for tips on PCB layout
https://www.douyin.com/user/MS4wLjABAAAAsrnydfX_gbCgGmRky_QT9Wb2DWgu3HW4-OZdRTNBeYxiiXZc4KSjrQEkq0Rp1N6v?modal_id=7350684535358590219&vid=7370001496252894518

[girishv]

Here is the revised layout. I have tried to follow the layout guidelines in the datasheet.

Please review and suggest.



Note: I have intentionally skipped adding stitching via's for now.

[T3sl4co1l]

Please ignore this post. I am revising the feedback circuit layout.

Here is the revised layout.

(Attachment Link)

I tried to worked on suggestions by @Tooki and @Harry_22 to keep the switching current traces short. I am not sure about layout of output capacitors. Please suggest.

@T3sl4co1l I can remove the ferrite bead if needed.

I'm afraid this is objectively worse than the initial case.

The caution with ferrite beads is more that it might do nothing (saturated by DC current bias), or make overshoot worse (more inductance --> more ringing on/between bypass capacitors).  The solution is 1. use an inductor (basically a ferrite bead, with enough air gap not to saturate at rated current), and 2. dampen the network with a lossy bulk capacitor in parallel with the bypass cap, typically using an electrolytic of 10 times the ceramic cap value.

You may find this of interest:
https://electronics.stackexchange.com/questions/713381/correct-placement-of-series-ferrite-beads-to-avoid-dc-disconnect-during-power-cy/713473#713473

Here is the revised layout. I have tried to follow the layout guidelines in the datasheet.

Please review and suggest.
: I have intentionally skipped adding stitching via's for now.[/b]

This is better.  Connectors on the same end of the board reduces ground loop EMI between them (this will be improved if capacitors are placed near the connectors, preferably with small inductors between existing net(s) and capacitors; improvement may not be necessary to meet commercial levels).  C3 doesn't need a polygon on it, it can be routed by trace and vias, and this allows GND to pour fully around U1 to reduce GND impedance.  Likewise the SW polygon on L1 isn't doing much, and a little more ground could fill between it and +5V.

This leaves room around all +5V, SW, and the general regulator area, to fill with stitching vias -- "fill" is a rather liberal term, but just one every 5mm or so, plus priority near critical GND pads (U1, C2, C5), will be fine.

Tim

[girishv]

@T3sl4co1l, thank you very much for all the help.

Here is the revised layout with Vias placed.

[Harry_22]

It is better to take output voltage from the capacitor.

[T3sl4co1l]

It is better to take output voltage from the capacitor.

Won't actually make a difference. There's no ground poured inbetween so there's mutual inductance and what's saved is induced right back in.  Arguably the field underneath the inductor is likely to be worse than the tiny stray (~5nH?) from left side of the pour to bypass caps.

Tim