4-Layer LM5175 PCB Review

[bbqstingray]

Hi everyone or anyone out there,

I have been trying to build a 4-layer LM5175 Buck-Boost converter input 6-36V, output 12V 6A, supplied from a battery.

I tried to layout to the best of my abilities but if anyone has the time
Could you please have a look at the board and give me some advice?
I would much appreciate it. 
   
LM5175 datasheet
https://www.ti.com/lit/ds/symlink/lm5175.pdf?ts=1633565737073&ref_url=https%253A%252F%252Fwww.google.com%252F
Attached are the schematic and the gerbers

Cheers,
Bbqstingray

[thm_w]

Whats the point of the split in the middle on the bottom layer?
Can post png screenshot of the PCB top/bottom if you want more people to take a look at it.

[bbqstingray]

I was thinking that separating the digital and analog signals needed separate grounds to would reduce further interference as they have separate return areas (although typing it out now makes me think this was a silly idea).


Here are the screenshots of the PCB
Layer 1 - Top Layer Signal
Layer 2 - GND
Layer 3 - Vout
Layer 4 - Bottom Layer Signal.

Thanks for the help

[OamSlaugh]

Hey Bbqstingray,
Thanks for posting the images.  A few comments from my side:

Creating split reference (gnd) planes is a tricky job and I would say don't do it unless you have a concrete reason.  In this case even in TI's schematic/layout example they just connect the AGND directly to PGND.  In reality though you have a full plane on Layer 2 so this isn't really a split.

If you did need to split planes sometime in the future, this is normally done by using separate Gnd symbols in the schematic.  These would be connected by an inductor to keep the same DC level but isolate high frequency currents.

The trick comes when you have a signal trace that crosses over this split.  You need to consider that this signal carries a current which needs to have a return path through the reference plane.  If there is a split or slot in the plane this return current needs to take the long way around, which causes a larger-than-necessary current loop that contributes to electromagnetic radiation or susceptibility.

Your ISNS+ signal on the bottom layer is doing something like that.  If you did not have a solid plane on Layer 2 the closes return path would be through Pin2 of the output connector.  This would make a small antenna to pick up extra noise for the input of your current sense amplifier (the opposite of what splitting planes is usually expected to do).


A couple of other things I noticed while perusing:
1. Normally the feedback point would be after the output current sense resistor.  It is good to also have some of that capacitance after the resistor so that it is less isolated from the load.  However since it looks like you are going to have an external output harness this will probably make little difference.

Personally I avoid resistance values above 100k when possible and would scale down the dividers to something lower.  It makes the design less sensitive to leakage currents, moisture, etc.

2. The big one for switching regulators: switch loop area.  The loop area for the current that travels through the inductor should be minimized to reduce radiated emissions from the design.  For example you could modify the orientation of the FETs so the inductor vias can be directly between the high and low sides.  Then the inductor could be placed directly underneath the FETs for a more compact layout.

Additionally the excess area for the switch nodes on Layer 1 should be removed.  Excess copper on the switch nodes (beyond what is needed for the load current) just adds more parasitic capacitance which causes ringing during switching and more radiated emissions 


That got out of hand , hopefully it points you where you want to go.

Cheers,
Oam

[bbqstingray]

Hey Oam,

Thank you so much for replying back and giving such great feedback.
This helps a lot thanks. 
 
The general layout example for the LM5175 shows copper areas were used for the switch nodes. 
Is this meant for heat dissipation? and is there a tradeoff between increased ringing and thermals?

Thanks again Oam.

Cheers, 
Bbqstingray

[tooki]

FWIW, I would look at a) any evaluation kits TI offers for the part (you can download the schematic, PCB layout, etc for free), and b) what the WEBENCH Power Designer tool spits out. (That tool lets you parametrize, customize, and simulate a design, and it produces a PCB layout for you.) You’ll be hard-pressed to design it better than that.

[tooki]

I actually took a quick look at the LM5175 in WEBENCH, and your selected parameters won’t work: above 3.8A output current at 36V, it overheats. Reducing the output current from 6A to <3.8A, or reducing the maximum input voltage to under 35.8V, lets it function. (The newer LM5176 supports your parameters, by the way.) While this may be caused by the particular selection of other components (like MOSFETs) in the simulator, it’s just a potential “gotcha”.

Do you really need that massively wide input range??

FWIW, this particular chip has several different eval boards available, optimized for different things. The WEBENCH design basically corresponds to the “standard” eval board. I did notice that the WEBENCH design seems to have some minor errors with the current sense lines — it’ll work, but they’re actually shorting the ground side to the ground plane, accidentally negating the purpose of the kelvin connection. So I’d fix that.

[OamSlaugh]

If you want to keep a larger copper area for thermal reasons you can cut out the Gnd and power planes underneath to get rid of the parallel-plate capacitor effect.  You could also stack copper area for the switch nodes on the internal layers to keep some metal mass while reducing the surface area.  Honestly if this is just a personal project you will probably be happier prioritizing thermal over EMC, especially if you aren't a fan of FM radio

above 3.8A output current at 36V, it overheats

Since the LM5175 uses external FETs I'm guessing that Webench is balking at the switching losses in Q5 at max Vin.  The device itself shouldn't care about the load current beyond reading the sense resistors, or take on any increased internal power with respect to load.  When I ran Webench at 35V / 6A for the LM5175 and 36V / 6A for the LM5176 I got completely different FETs in the BOM, even though they should be very similar (attached)

They are also seem very mismatched: the LM5176 example has M2 with a higher voltage than M1, and M3 is rated for double the current of M1? (at nearly double price too)

Maybe I'm just in the camp that doesn't trust the auto tools, but this could be one of those areas where Webench doesn't give the best result, or it's trying to sell more TI FETs...

Cheers,
Oam

[tooki]

Yeah, most likely. I’d go by the design of one of the eval boards, since that’s been designed to show off the component at its best.

[Twoflower]

Do you plan to use a metal housing? In that case the grounded mounting-holes might contradict the split ground-planes. I probably would only use one grounded mounting-hole or none.

[bbqstingray]

Hi everyone, 

@Twoflower, I am planning on placing a metal housing but not until I've sorted the kinks of the PCB. But that's a good point about the mounting holes, thanks for the heads up!

@Tooki, I originally designed this around the LM5176, which i think is the successor of the LM5175, but stock for LM5176 has dwindle in my area.
That being said the datasheet says the typical application is for this sort of output.  Thanks for checking it though.


@Oams, Testing the WebBench showed a lot of variations for MOSFETs and components and i figured that I could use the same type of MOSFET. Thanks for the help, it is very much appreciated.

Cheers,
bbq