pmos latch switch

[Talseven]

We have a power distribution board for our robot that is responsible for switching power to various modules (controlled via stm32 gpio). The first implementation was pretty simple. we used a high side pmos switch with an nmos controlling the gate of the load switch. Gate of the nmos being directly driven by stm32 (bss138 logic level nmos). The problem that we were facing with this was that whenever the board was reset due to lets say a watch-dog event or ota firmware update. The power to the entire robot was disconnected. So we wanted to build a latching circuit with an on and off circuitry.
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The circuit isnt working as intended. The switch M3 is on by default and when M2's gate is driven high the switch is turned off but the latching action isnt acheived. As soon as the M2 gate is let go, M3 turns on again. M5 is actually CMPDM0072A and not BSS138. The circuit works fine on ltspice.

At turn on, i know that the pmos is switched on momentarily due to the input voltage appearing across Vsg. Is this the reason why the M3 is turned on by default? since R5 feeds the output voltage back to the gate of M5. But this doesnt explain the turn on behaviour after the M2 gate is driven high and then low, the gate of M5 goes to 1.6V , M4, M1 and M2 are off.

[Kalvin]

Not answering to your question, but something interesting is going to happen if you drive M1 and M2 "on" at the same time.

[Talseven]

  Thank you for pointing it out.
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