Recently I keep thinking about do and don'ts of polygon pours on PCBs.
There are interesting articles about various issues, where eg in the chamber someone tests different PCB variants and compare how the placement of components, tracks routing, pours etc. affects the emission. There are also case studies, where the influence of some factor (eg the shape of the pad) is measured across specific parameter (eg the voltage drop across the shunt resistor).
But I have not been able to find such a study about polygon pours yet which I find very interesting.
Interesting idea. To me, I don't like it as a comparison, because -- while, ultimately, you're merely changing the impedance and coupling between traces, the fact that you're changing it so dramatically (from sizable-fraction to ~negligible) presents more of a structural change, than a continuum change.
Consider a PCB as a network connecting pads (ideal ports) together. The coupling between any given pair of ports, at any frequency, is a matrix. Presumably, we want direct connections to have nearly 1.0 coupling, and 0 elsewhere. In reality, there will be nonzero coupling. In some cases, it may be large enough to be significant, or useful even (a microstrip coupler). If the intent is still to have zero, then we can't simply hope for the best!
Practical reasons introduce nonlinearity to an otherwise linear situation. Consider a pair of oscillators at close frequencies: if poorly shielded, they will lock together. We went from an intended design to an unexpected result, due in turn to the failure to anticipate how much shielding was necessary.
Ultimately, the
only thing you're doing, is putting down metal to block waves going through some path. There is no such thing as an electric or magnetic field insulator: you cannot have a permittivity or permeability less than 1 (except in contrived circumstances -- metamaterials). So the only thing you can do is block them. (You can insulate DC, but DC is boring. By definition, nothing
happens at DC. And AC cannot be insulated, as such.)
Which necessitates a current flow to block magnetic fields (Faraday's law), and a charge to block electric fields.
A metal carries both.
Metals also absorb. They have finite resistivity, so waves penetrating into them will get weaker and weaker before coming out the other side. They also have very high index of refraction (dominated by resistivity, which manifests as imaginary permittivity or permeability), so they are very good reflectors.
(Superconductors are a special case, where the resistivity is practically zero, and the effect is total reflection. The difference is they are very good reflectors all the way down to DC.)
Note that this is a perfectly equivalent description of wiring: in that case, you are shielding some signal from going in any direction but the direction of the wire. A design that needs low coupling between wires, also needs a lot of metal between wires to shield them. So really, you need to apply both approaches for a good design.
1. The first thing. Is the hatch polygon of ground functionally any different from the solid one? I use solid ones myself, but I have a friend who passionately uses hatched polygon pours on the PCB. I heard that hatched polygon pours were easier to manufacture and full surface was more difficult to obtain. It could be true in homemade thermotransfer and etching, but was it also true for mass production? I do not know. Other differences are heat capacity and impedance. But I am not sure if using hatch was popular because of them.
Have you met hatch polygon pours in any modern, mass-produced circuit? Or do you know specific cases when it is more desirable than a solid plane?
I've only seen hatch in a multilayer digital logic board. Probably they didn't care about its exact impedance, and had higher priorities, like manufacturability or planarity. (Or maybe it was thieving that I was seeing -- the opposite of hatching -- I don't remember.)
A trace running over a hatched pattern (not aligned to the grid lines) gives what's called an electronic bandgap. Less fancifully: a bandstop filter. Periodic gaps in the ground are equivalent to periodic narrowings of the trace, giving a transmission line lowpass filter. Except, it's only LPF around the 1/4 wave frequency, and it becomes transmissive again by 1/2, and so on (roughly speaking), hence it's only a bandstop function.
Where does the energy go? Well, if the hatched pattern is shielded by another layer, it doesn't have anywhere to go, but if not, you've got a leaky ground, and some wave energy radiates.
2. Does in the multilayer circuit, where we have power and ground planes inside, pouring the signal layers makes sense?
For example, part of a Rigol DS1054Z pcb doesn't have polygon pours on signal layer...
https://obrazki.elektroda.pl/8796583200_1540851781.jpg
... but another part does 
https://obrazki.elektroda.pl/7228270900_1540851827.jpeg
In what aspect adding ground planes (pours) in multilayer pcb will help? Because I know that it can spoil, for example, the impedance of trace when it is too close. Or increase the trace capacity. It seems to me that for these reasons, the ground polygon pours on the signal layer was abandoned in selected parts on the Rigol pcb.
Here is the question for antenna specialists Does a trace above the ground plane form an antenna? Or this plane shields the trace and "spoil" the antenna?
I rarely pour outside layers, partly because I'm almost never working on designs like this, and it's an awful hassle to place components AND vias AND copper on four (or more) layers and resolve connectivity (and good grounding, and good thermal connection if the motivation is more for thermal conductivity rather than EMC performance).
What does it do? More metal.
Consider one trace over a ground plane. It's surrounded by metal on almost an entire half-sphere. That's good shielding already, so the coupling to free space is small. Yes, you can still make an antenna this way, but the low coupling dictates equally low bandwidth: you have to make a resonator to drive up coupling at one particular frequency. And then your efficiency sucks because of board losses.
Consider one trace over, and within, a ground plane (i.e., surrounded with ground on the same layer: coplanar waveguide). It's surrounded by ground on slightly more than a half-sphere, so the shielding is even better.
That's basically all you get.
The change in trace impedance, and increase in capacitance, are just derived aspects of the general case: a reduced trace impedance for a given width. This can be advantageous as you can use a slightly narrower trace for the same impedance (assuming it can still be fabricated with good yield), and you have ground traces shielding between the signal traces. The total width probably increases (for a given bus of traces, at the minimum design rules, you've doubled the number of conductors because every other one is ground), but when you need that isolation, it's more effective than simply putting distance between microstrip traces.
So, it seems likely what Rigol was doing, was getting that extra bit of shielding, where they could, basically for free -- no parts cost, no shield cover, just PCB fab -- and where it was easiest to do so, i.e., where nearly no components are present. Whereas, under the RF shields, there is a ton of components, and even trying to pour ground between them would be a waste of time!
3. Planes and via stiching..
This fragment has loosely placed polygon pours (without vias, like in lower left corner), and I do not believe that underneath there is no ground plane to connect it in several places In other places, they use many vias...
Personally, I stitch at no more than ~2cm between vias, near circuitry. (Far from circuitry, I don't really care, and I'll sprinkle a few in, particularly at corners and long stretches.) That's probably overkill for most, but would be marginal for power switching, higher speed (say 74LVC family and up) logic and RF.
Via density is proportional to upper cutoff frequency times desired attenuation. You might need a dense, multi-row via fence to ensure adequate isolation between traces in an RF mux (>100dB isolation), but digital logic isn't going to give a shit if you route microstrip together (trace separation ~= height above ground plane giving maybe 5% coupling, not even enough to screw up a logic threshold -- assuming it's not a timing-critical clock trace or something, mind).
Tim
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