Proper Layout Check for milliohm meter

[Hiemal]

Hi everyone.

Been working on a PCB for a milliohm meter. Going to work on 1 li-ion cell.

Has two DC-DC converters; one ups to 6v, which then goes through a linear reg down to 5.1v to feed all the circuitry.

The other is a buck, which feeds the shunt/current source. Drops down to 1v to reduce mosfet power dissipation.

Uses an MCP1501 as a voltage reference, 2.5v which goes through a 2.4M / 100k divider to give 0.1 volts. The multitude of resistors is due to 2.4M being nonstandard, so I had to make it out of several. They're all 0.1% resistors and low tempco. This is then fed into the GS8552 op amp, which then drives the FET to form a current source.

An MCP3421 18-bit ADC is on board, to facilitate measurement, which gives info to an arduino.

So, my questions...

1. Is a guard ring necessary in this case? I put one around the inverting input  of the op amp, up and around part of the resistor divider, shown in the photo where it says "guard?". Is this not enough or is it "pointless" given the current design?

2. Are my thermal relief cutouts helpful? I tried isolating the more sensitive parts of the circuitry away using the cutouts.

3. Should I be separating the ground down by the DC-DC converters how I have? The top layer ground plane is separated into two segments, one for the DC-DC converters, and the rest for everything else. The bottom layer GND plane is 1 piece, no segmenting.

Otherwise, are there any other glaring layout issues anyone sees? One of my other concerns is having the I2C traces going right underneath the 5v rail on the top of the board.

If there's anything else I can add or whatever to help, please let me know. And please be gentle, I'm very much self taught in PCB design/layout, and I know I still have a lot to learn.

https://snipboard.io/aALw8i.jpg

[trobbins]

BD3508 as a boost IC ?

Given your incentive to reduce parasitic noise etc, I could make the following comments:

Buck IC could have input bypass cap located better to minimise switched current loop length around that device from VIN to GND, and that current path could use a separated gnd trace (ie. don't use a common portion of either VIN or GND trace).  Is the input supply bypass cap sufficient to minimise switching ripple back through the battery? Can the buck inductor be moved down towards the IC (to move it further from anything else), and can its trace be separately shielded by a ground that just connects back to IC GND? The regulated buck output supply connection point for load and feedback should come from the C2 pad, not from the inductor pad.  The C2 gnd pad should also have a separate trace back to IC pin 2.

Boost circuitry would appear to benefit from similar comments. 

Are your smps inductor part choices appropriate for the switching frequencies (buck uses 1.5MHz).

Does the GS8552 have a local supply rail bypass?

Do you have a schematic, and a bottom pcb view?

[Hiemal]

Hi Trobbins, thank you for your feedback!

Here's the changes I made per your suggestions; the only thing I didn't do was shield the inductors with the IC GND; felt like it was gonna be too loopy around and couldn't get it to work right. I also took some time to check out the manufacturer's recommended layouts, and tried my best to copy them.

Yes, the inductor part choices are appropriate, taken from their respective datasheets, as well as capacitor values. All IC's have local bypass caps. I also goofed up on the name of the boost IC, it's actually BRCD3508, 1.2 MHz boost. Alternatively, I also have more efficient/quieter boost IC's with the same pinout that I can swap in if need be. The BRCD3508 is just what I have a ton of, since they're inexpensive.

I do not have a schematic, it'd take me a while to piece one together. I also linked a picture of the bottom PCB view.

Again, thank you for your help with this, I appreciate it.

https://snipboard.io/8tHq3V.jpg

https://snipboard.io/cLsT2u.jpg

[trobbins]

Just my 2c:

The rearranged TLV62569 appears to me to be much better.  My original comment about the inductor trace shield was about the 'hot' trace going to the inductor rather than shielding the inductor itself - and that trace is now very short, and that whole smps is as distant as practical.  The only pedantic point to make is for the IC gnd terminal to be best common connection point for input and output side supply current loops.  If you only had one smps then the batt neg terminal would best go directly to that common connection point, however you have two smps to connect to, but it is still worth imho trying to make a local batt neg land from the batt neg terminal out to two smps common neg points, and not let currents in those two loops pollute the negative/gnd land used by the remainder of the pcb load side circuitry.

Those same comments would similarly apply to the boost, although I'm guessing the boost power requirement is significantly less than the buck?

Can you use the bottom layer to provide a ground shield under each of the smps regions, with a single point connection to the relevant IC gnd point? The intent is to circulate parasitic capacitive currents from parts with each smps' circuitry back to that smps gnd point.

[Hiemal]

Yes, the boost converter's load requirements are a lot lighter, it's really only there to power the analog circuitry, and the arduino. The LCD screen might draw a bit more current though, not sure.

Meanwhile the buck converter is gonna be connected to a 1A CC source.

Here's the updated ground plane under the SMPS section, with single attach points.

https://snipboard.io/4LZan9.jpg

My only other lingering question is if it's okay for the 5v rail to wind around as much as it does? Here's a pic with the trace highlighted to show what I mean. Additionally, is it okay to have the 5v trace right above the I2C communication lines?

https://snipboard.io/fw2YKu.jpg

Otherwise I think that's it, if you think the rest of the layout looks alright as far as my techniques go. 

[trobbins]

Given I'm just having a quick gander, it would certainly be easier with a schematic (and perhaps even a design summary such as allowed for DUT range and LSB-noise floor levels), and the full front and rear pcb views - maybe the same issue for other viewers.  Also I recall some of the IC overlays don't clearly show pin 1.

[Hiemal]

Sure thing, I'll give creating a schematic a go tomorrow. And, admittedly, there actually isn't any "design summary", this is entirely a hobby project and I don't really have any ideas in mind, other than making it as accurate as I can reasonably do so.

I know that's kind of open ended given that a lot of people on here design for companies and whatnot.  Either way, I appreciate any help I can receive alongside any pointers, I always love learning more about how to do things "the right way" if that makes sense.

[Hiemal]

Here's schematics of the board "segments", with each distinct component in different photos. Hopefully that makes it easier to read and understand. 

Let me know how I did!

[trobbins]

Just my 2c.

The opamp schematic is different from pcb.

Apart from part selection, is the performance of the voltage comparison between 0.1V ref and shunt terminal voltage a key issue for you?  If so, then the gnd points for the 0.1V ref (ie. R1 100k pad) and shunt pad should have minimised chance of gnd plane noise adding in to that comparison.

You are only showing a 2 terminal shunt part on the pcb.  The ungrounded end of the shunt may benefit from lowered thermal resistance, and a psuedo Kelvin connection. Eg. use some centrally located vias and make the sense trace connect on the rear side.  You may better balance the thermal resistance provided by each shunt pad by increasing the trace width over to the RES terminal, such that the terminal performs some heatsinking (or alternatively flip the shunt 180 deg).

Did you consider connecting the VM+ and VM- traces to the RES terminals via protection resistors, so that those ADC inputs weren't floating ?

Did you consider including a protection zener on the FET gate-source ?  R10 is best placed close to the FET gate.  (ie. shit happens with FETs when you least expect it)

[Hiemal]

I double checked the op amp schematic and I'm not sure what's different than the PCB.

I'll go ahead and make the changes you suggested for the shunt; I'm not sure why I didn't even think of a kelvin connection! With what you're saying about the GND points between the shunt and ref, do you mean I should try to make a direct trace connection between the two instead of a big chunky ground plane?

The VM+ and VM- traces, along with the RES terminals are meant to go out to kelvin sense clips, so they shouldn't be floating during normal usage.

I didn't consider adding a protection zener to the FET gate/source, since the op amp should only really be capable of +5v. I'll go ahead and move R10 closer to the gate as well.

[trobbins]

These are all just suggestions - you don't need to include - I'm just noting those things that would concern me, and even then I am just glancing at this.  PCB design is often a collections of compromises, so you are the one to rationalise what is worth trying to modify or not.

I was looking at the older total pcb image, not your latest snips - perhaps that was the issue with the opamp.

Note that you can still use remote Kelvin connections - the concept of having some on board resistors is sort of like remote sense terminals in a power supply - any remote direction of voltage measuring clips just shorts out the on board resistors.  The intent of these resistors and the FET zener are just to alleviate damage from accidental situations.

It can be worthwhile appreciating what ground current loops occur around the pcb, and if any loops 'cross paths' or use common sections of ground fill - sometimes noise in the ground plane can couple in, although that likely requires a deep-dive assessment of performance.

Have you breadboarded this up - especially the ccs ?

[trobbins]

It also may be worth allowing for an RRC network on the ADC analog input, to provide some additional noise filtering of the external signal, and to control the impedance of the voltage presented to the ADC input, given it is an 18-bit delta sigma converter.