PWM controlled PowerSupply PWM buffer

[janekivi]

 Probably the time of uSupply project I did think to make mine too.
And time to time I dig it up and make some changes before packing it away again.
So far it is ver.7.5 or 6 and end is not seen. Some things are working great and then
some go worst.
 Last(latest) problem now is PWM smoothing. I have 5V PWM output from ATMEGA and
over the years I tried options A, B, C, D...
 A - working but very slow reaction to the encoder and settling time
 B with D - working good and quick but noise from ATMEGA is getting through
 C with D - very good but now there is nonlinearity in the middle

 I have set in CPU 1 PWM step 1/3mV to get after 3 times gain op amp 1mV output on LT3081.
All is working good but with best buffer (C+D) with calibrated power to eliminate CPU power
noise I lose 1.3mV in the middle of the 5V range of PWM which translates to 4 mV missing
in the middle of 0...15V LT3081 output. But with B+D combination output is linear and output
voltage is correct through the range. Only it is noisy, especially when CPU sending something
to the display.

 It is 20MHz CPU and that PWM is then 1325Hz. Because of swinging CPU power I need to calibrate
and buffer PWM output somehow without losing it's linearity. Why there is nonlinearity? What to do?

[MariuszD]

PWM filtering is a cheap and simple DAC. When you start improving it, it will stop being cheap and simple, but it won't reach the parameters of a COTS  DAC  IC.

I don't know what "very slow" means to you, but what you have achieves 99% in 240ms. By changing the RC values to reduce the load between the stages, this time can be reduced to below 100ms.

By reducing the attenuation or increasing the filter order, better times can be achieved.

I don't see MKT capacitors on your board, Class II MLCC (X7R,Z5U,Y5V) capacitors are nonlinear, maybe this is the cause of the nonlinearity in the ripple cancelation circuit. Piezoelectric effect also occurs in such capacitors, which can worsen attenuation.
Another possible cause of the non-linearity is the fact that the resistance of the digital outputs in the low and high states is different. But for now, I don't feel like analyzing it in detail. I'm just writing about things that come to my mind as a topic for further discussion.

[PCB.Wiz]

It is 20MHz CPU and that PWM is then 1325Hz. Because of swinging CPU power I need to calibrate
and buffer PWM output somehow without losing it's linearity. Why there is nonlinearity? What to do?

As in #1, non linearity is unexpected.

Suggestions would be to change to a better opamp, allowing smaller better dielectric caps.

Note the PWM cancelling approach, is largely a mirage, the added RC element is just as good or better adding another filter stage.
As shown in #1, the best analysis is to run step response and zoom into the ripple, and you want best step:ripple  trade off.
Also as shown in #1, scaled R filter stages give better step response than the generic R-C-R-C-R-C.
You can also use an active filter, to get fastest settling into a (say) 1% window.

If you have the MCU resource spare, a bigger leap would be to use two 7 bit PWM (or 8+6 etc) and mixing resistors, which can greatly increase the PWM frequency.
For a power supply, you probably want extremely low PWM ripple feed thru, as that could get very confusing down the track.

[PCB.Wiz]

Last(latest) problem now is PWM smoothing.
 It is 20MHz CPU and that PWM is then 1325Hz.

I did find this in my notes

http://sim.okawa-denshi.jp/en/Multiple3tool.php

This filter design has two caps to ground, before the opamp, so it has good stop band for the high spectrum of PWM.

eg If I create a 30Hz filter with 0.75 damping, it gets to the right ballparks.
Gives
R1 = 91kΩ
R2 = 300kΩ
R3 = 750kΩ
R4 = 390kΩ
C1 = 0.1uF       <- you can set these two - 100nF NPO/COG are available
C2 = 0.022uF   <- you can set these two
C3 = 0.0033uF

Gives amplitude peak of
0.035901668288844s,-1.0054576721175  final value = -0.99744237589753  so that's a small ~ 0.80% overshoot.
It crosses -1% threshold  at 0.028721334631076s,-0.98791604261085

Attenuation at appx your PWM value is
1359.3563908785Hz = -99.336649856933dB

It appears you can get ripple lower than your step size, if you are ok with a ~29ms settling time to 1%.

[Doctorandus_P]

Very good linearity can be achieved with filtered PWM. Back in the '80-ies a bunch of 20 bit precision voltage generators were based on PWM techniques, but to get to that resolution the whole design is not trivial anymore. It will for example never be better then the (static) voltage reference used. To get a decent response time with low ripple, you want a high frequency PWM output so you have a lot of headroom for the filtering.

There are also several articles posted on the EDN website about reducing ripple from PWM outputs. But it's always a tradeoff between remaining ripple, setpoint accuracy and regulation speed.

[PCB.Wiz]

http://sim.okawa-denshi.jp/en/Multiple3tool.php

R1 = 91kΩ
R2 = 300kΩ
R3 = 750kΩ
R4 = 390kΩ
C1 = 0.1uF     
C2 = 0.022uF 
C3 = 0.0033uF

I entered those values into spice as a double check, it comes out quite close

Spice checks:  Overshoot  (5.5027255-5.498713)/500m  = 0.8025%  ~ 36ms
Rise time to 5mV/1%  ~ 29.93586ms
Attenuation : Stopband  1/14.3u  = 69930 (97dB) reduction.  predicted 99dB is ~89125
14.3uVpp stopband ripple is little changed with OpAmp 1MHz - 50MHz

[MariuszD]

Asymmetry of the output resistance in the H and L states will cause nonlinearity. I calculated it, inserted the output resistance of the HC gate obtained from the Nexperia 74HC04 IBIS model Rh=59.6Ω Rl=45.5Ω, and got this error graph. Maximum 1.4mV

According to the IBIS Atmega model, the resistances will be 19.9Ω and 18.3Ω, which will result in a non-linearity error of 0.2mV. That's why  B with D has better linearity than
 C with D.

[janekivi]

 Thanks for many ideas here.
 It intended to be easy and simple and cheap and good... but I did select
bit better arduino CPU where you can say whatever PWM you like (max 16 bit)
and it is set to 15099 to get 15100 mV exactly. Idea was to use those laptop
19-20V PowerBricks and with pulse preregulator this is max to get out.
INA190A2 shows 0.0001A using (noise) average calculations and
ADS1115 is showing 0.0001 V the same way.
Because of some errors you know then how far away the actual 1mA or 1mV is.
This all works good and I can't afford 1mV errors at output any more 

So, 7805 is powering the system and its output raises 10mV during first 2-3 minutes.
PWM raises too and output 3x10 then. I get rid of CPU power noise only by buffering
its PWM outputs and then can smooth them out what ever best way.

Now is the good buffer question which power I can calibrate with TL431 for example.
I can't calibrate CPU power, because of display traffic and everything else it is affecting
PWM amplitude anyway.

 How to buffer PWM without nonlinearity? How to find best IC or even discrete circuit?

[MariuszD]

How to buffer PWM without nonlinearity? How to find best IC or even discrete circuit?

You need to use a buffer that has the same resistances in the H and L states. Since it may be difficult to find such a component, I would use a circuit that has separate outputs for the drain of the high-side and low-side transistors and adjust the resistances with external resistors. I saw something like this in MOSFET drivers, for example, UCC27511 or UCC27531. You could supply such a driver with 15V, there would be no need to amplify.

Looking at the UCC27511 documentation, approximately 4.6 ohms will be needed for the OutL output.

If you increase R83, the impact of output asymmetry will be smaller. You can also use the 74LVC1G17 buffer; the resistances according to the IBIS model are 9 Ohm and 10 Ohm.

[PCB.Wiz]

How to buffer PWM without nonlinearity? How to find best IC or even discrete circuit?

Increase the load R and use a better opamp are two easy steps.
Some designs use a SPDT switch, where you can add a small trim R in series with the low-R side to balance.
Pick a fast SW with somewhat good end-point R matching.
eg Diodes Inc 74LVC1G3157 shows typically 5.5Ω  at both end points of 0V and 4v5 with Vcc=4v5, and Tpd  typ 2.9ns
Nexperia 74LVC1G3157 is typically 5.8Ω and 4.9Ω
 
If you use single gate parts, you can also add the trim R to the Gnd leg, since gnd = NMOS source.

[janekivi]

 Got some 74LVC2G17GW and seems like they work very well in diagram C followed by D which is currently in use.
It supposed to do quick work with slow PWM and found that in "The-Art-of-Electronics-the-x-Chapters.pdf" 4x.25
and S. Woodward, “Cancel PWM DAC ripple with analog subtraction,” EDN, 28 Nov 2017
It is used in EEZ_PSU too I believe.
 Everywhere is some good stuff and my project directory is over 400 MB of pdf and diagram images and ideas.
Something I found in Scullcom Millivolt Meter MK2, there was that additional decimal place calculation.
(OK, actually it was in MilliVoltMeter334.ino but can't find it online right now.)
(There are updates MilliVoltMeter336.ino)


 But now I must correct PCB layout and find better parts because heating is bit of an issue around OpAmp
like R92 is too close to 7V pulse PreRegulator capacitor and some TrimPots are probably affected too.
Haven't find good ideas for digital calibration there which would be best - like selfCAL...

 To make it cheaper it has 100x100mm PCB limitation of course and cooling must be in one side.
It has all usable CPU connections for different displays and keyboards but haven't implemented
output relay at this time. Actually I lost some mV already from LT3081 leg to the 25mm away
to the output pin but best connection is his heatsink plate?

 But about that better OpAmp in LM358 place- I tried some and it can't be too good because
now it gives better current limit reaction and no overshoot (but some can be better, sure).

[PCB.Wiz]

Got some 74LVC2G17GW and seems like they work very well in diagram C followed by D which is currently in use.
It supposed to do quick work with slow PWM and found that in "The-Art-of-Electronics-the-x-Chapters.pdf" 4x.25
and S. Woodward, “Cancel PWM DAC ripple with analog subtraction,” EDN, 28 Nov 2017

That EDN article has some flaws.
The PWM cancel needs another RC, and that RC can be better put to use in another filter stage.
You need to compare rise time with ripple, to properly evaluate the results.
eg for equal ripple outcome, spice shows that EDN (2023 improved) PWM cancel (2R 2C) has Tr = 5.212ms, whilst a buffered 2 stage filter (2R 2C) is Tr = 3.815ms
There is a thread on this here somewhere
Addit
https://www.eevblog.com/forum/metrology/pwm-new-article-from-s-woodward/