Hi All,
I'm trying to reverse engineer a proprietary, but VERY SPI like databus. I'm about 90% done, but there is one aspect of the last 10% that is really slowing me down.
With this SPI-like databus, the clock signal under one circumstance will drop to ground for a short period of time, which is NOT intended for a logic change on either the MOSI or MISO line. It is for another purpose - to signify a very accurate timing point.
Every logic analyser program I've tried registers the clock fall and rise, and in turn, logs a bit where it shouldn't. It thereby, shifts the calculated byte structure left (off the real sets of 8bits) each time it happens, so the supposed byte is now calculated using the dodgy "bit" that it registered from the non-data-structure clock cycle, and the first 7 bits of the correct byte it should be calculating. This then makes up the 8bits for the byte it works out, ditching the last bit which should have been part of it. This last bit is then used for the first bit of the next byte, and on it goes....
This can happen multiple times in a datalog, each time making the calculated bytes further 1 out of sync each time there is a registered dodgy bit that shouldn't have been there.
Right now, my only way around it is to extract the HEX data into CSV, note where the dodgy bits were registered, then pass it through a python script which changes it back to binary, links all the bits into one big string, deletes the offending bits which caused the problem, then breaks it into 8s, turns it back into hex, and puts it back into comma separated values. This works, but it's time consuming and tedious noting down all the time signatures, and byte numbers to pass into the python script...
If only there was a logic analyser program that would let me flag a clock cycle as effectively being ignored for SPI analysis.
Also, because all the original byte "time signatures" are based around the shifted bytes, they're all wrong after the bad bit, and thereby useless.....
Any other ideas?
I'll post a logic analyser screenshot to give you a better idea what I'm talking about....You can see the offending clock cycle at ~5230200us
And yes, the clock dip is used for other purposes.
Richard