Decoupling chips with lots of power pins

[shadewind]

I'm trying to route a board which is using a TI Stellaris MCU in a 100 pin QFP package. There are about 13 3V3 power pins and add to that 4 VDD25 power pins which take their voltage from the LDO which is built onto the chip.

My question in this is how to go about with decoupling this on a two sided board. I understand that I should have one decoupling cap per power pin which would leave me with about 17 caps which is quite a lot to fit.

If I have them on the top side, there are problems to fit anything else if I want them close to the pins. I can move them away a bit but that would make the decoupling worse I suppose (how far is too far?). Another alternative is routing most of the signals through vias in the center of the chip but is this good for signal integrity (there is, for example, an on board ethernet controller that I'll be using)? A third alternative that I've heard about people using is placing the decoupling caps on the bottom of the board right underneat the chip. What's the correct way to route using this method?

[RayJones]

Seriously, any board using such high density devices should be 4 layers at the minimum.

[shadewind]

Yes, probably but I'm going to try anyway. I'd rather try, fail and then learn something in the process.

The problem with cap placement would still remain if I had more layers, even if it would be a bit easier given the increased routing options.

[Zad]

Perfectly do-able on 2-sided. I have used higher pin count chips than that without major problems. Sure, if it is a commercial design then you need 'enough' caps and tight impedance control, but for your own use then I wouldn't worry so much. It is not uncommon to put the caps on the groundplane layer, just try and make the via as close to the pin as you comfortably can.

[mikeselectricstuff]

The problem with cap placement would still remain if I had more layers, even if it would be a bit easier given the increased routing options.

Not necessarily - power planes have much lower inductance than tracks, so you can get away with fewer decoupling caps and/or you can locate them a bit further away.

As regards 2-layer routability, it's not so much about number of pins but number of different supplies, and flexibility of signal pin assignments for easy routing.
I've done 144 pin FPGAs on 2 layers & still had a decent groundplane.

[TheDirty]

Is there any IO left on that chips after all that?  Is this thing really 1/3 power and gnd pins?  That seems crazy, a throwback to old ARM7 packages.  An 80pin LPC17xx will have more available IO at the end of the day.

Anyway, ya, decoupling should not be hard at all.  Pretty easy actually if you want to go down to 0402 caps.  Get a nice small crystal.  That always is the most annoying for me is making space for the crystal.

[shadewind]

100 - 13 - 4 = 83

...of course there's room for I/O on 83 pins


But if I place the caps on the bottom side, I seems perfectly doable and I hardly have to do any weird things at all to make it work. I'd rather not use 0402 caps since it will be much harder to solder, though.

Anyway, I'll be pretty satisifed if I can get it up and running at all. If it works poorly, I'll have learned something anyway.

[Zero999]

Are you sure you need a capacitor for each power supply pin? That sounds overkill. Can't you just have a capacitor near each load of PSU pins? Using different size capacitors is probably a good idea, 100pF, 1nF, 10nF and 100nF so you get decoupling at as broader range of frequencies as possible.

[TheDirty]

100 - 13 - 4 = 83

...of course there's room for I/O on 83 pins

Your math doesn't include the gnd pins or you mistyped your original post.  I thought your 17 pins might have included GND, but you said you needed 17 caps, which would confirm that it was actual power pins and not power + gnd pins. If it does include GND pins, you only need 1 decoupling per power and gnd pair, so you would need much fewer caps than you mentioned.

I seem to remember some decoupling guide or datasheets recommending not putting your decoupling through via's, but I see it all the time with real world boards, so it can't be that bad.

[shadewind]

Never mind, my math is nowhere near correct, of course, but still, there's enough I/O left in any case.

Are you sure you need a capacitor for each power supply pin? That sounds overkill. Can't you just have a capacitor near each load of PSU pins? Using different size capacitors is probably a good idea, 100pF, 1nF, 10nF and 100nF so you get decoupling at as broader range of frequencies as possible.

You tell me
Am I sure I need a capacitor for each power supply pin? No, I'm just doing what I read on the web: One cap per power pin.

[Neilm]

It depends on the chip design. I have done design on FPGAs of that size so that is what I have for referance. For example an FPGA migh have 1 or 2 pins that power the core, the rest of the power pins would be for powering the external IO. Each of the IO pins might have to switch heavy loads at high frequency which would cause pulses on the IO power rail. These pulses might cause problems for the other things on that rail - or even the chip itself if the pulses couple into the core supply.

Chip designers have multiple supplies to reduce the number of IO ports that are supplied from each pin and to reduce the distance the power has to go on the silicone. As each pin can have the full demand, the chip suppliers reccommend a capacitor per power pin. As these are used in commercial applications there is no problem fitting this on the board if the designer uses 0603 or smaller caps. Clever use of power and ground planes can also add to the capacitance on each pin, with the power and ground planes acting as small capacitors with the larger caps a bit further away.

You would have to work out what your application requires. If you only have low frequency signals that don't have to have to switch hard then you would not require as many capacitors. If you have many high frequency signals then the opposite applies and you would need more capacitors - possibly more than the 1 per pin recommended.

Yours

Neil

Neil

[shadewind]

For now, it seems that I'll be able to fit all of the caps (one per power pin) if I have them on the bottom side without too many issues and that's with 0603. I think I'll be comfortable hand soldering that size so I suppose it can't hurt to try to have all of these caps on there, right?

[tyblu]

slightly off-topic, but..

Remember that if you have trouble with decoupling, one further step is to decouple both power and ground separately ... see Electromagnetic Compatibility Engineering by Henry W. Ott

[joelby]

Generally, you'll want to follow the chip manufacturer's guidelines unless you have a good reason not to. Typically these recommend not to put decoupling on the opposite side (for non-BGA packages, at least). Using a range of capacitor sizes seems to be the traditional way to go, though some testing I've read has shown that this isn't necessarily useful. Some of the newer FPGAs recommend using only larger (e.g. 1uF) capacitors.

0402 isn't too bad to do by hand if you have a good eye and magnifying glass

[shadewind]

TI/Luminary Micro doesn't seem to have a recommended decoupling scheme or I can't find it...

[joelby]

That's annoying. Try looking at some of TI's reference designs. I did some quick searching and they have some two layer designs that could be worth emulating.

[shadewind]

I looked at the reference design for Luminarys Ethernet connected intelligent display which uses a similar MCU to the one I'm intending to use and sure enough, they use much fewer decoupling caps, just a few of them per side and with different values. I'll try to emulate what they're doing.

[shadewind]

A question though... the reference design doesn't really have enough low value caps to cover all of the "sides" of the chips and certainly not enough to cover the all sides with both 0.01 µF and 0.1 µF. How should I place the different values? Should I just just distribute them to be close enough to all power pins or should I place specific values in specific places? Luminary doesn't really have any specific documentation about this.

[jahonen]

Recent measurements I made indicated that it is usually best just to just put N pieces of high capacitance capacitors parallel instead of different values for given package size. Logic behind this is that using same values avoids parallel resonant circuit formation, and thus impedance peaks. In other words, I'd put 2x100n in parallel instead of 10n and 100n, unless you want to "play chess" and have exact knowledge of spurious frequencies, so that resulting parallel resonance won't cause any problems and notches hit just the frequencies you are targeting to eliminate.



Regards,
Janne

[shadewind]

As always, you come up with relevant and informative responses to my posts, thanks a lot!

[TheDirty]

Despite using an 100pin LQFP, it looks like you are pretty green at this.  To break it down simply, you want 100nf caps as close to the power pins as possible.  You use one capacitor for each power/gnd combo, meaning if you have 5 power pins and 5 gnd pins, you have 5 caps.

Place the caps inline with the power delivery.  I've attached a sample of placement.

If you want to research it more later, you can, but this is all you need to know to get your board done and this is how decoupling is done on 99% of boards that you see with common non-BGA microcontrollers.  Don't worry about multiple cap sizes or multiple caps on the same pins at this point.

[shadewind]

Yes I am pretty green at this but I like to take on large projects when learning something new, just a bit bigger than I can currently grasp and research the rest. I find I learn best that way.

But wait now... one cap per power pin pair? That's would be 17 capacitors if you go by the power pins or 18 caps if you go by the ground pins. As someone else said here... that can hardly be what Luminary intended since it's not even in their reference designs.

This is making me confused. A lot of people keep saying "one cap per power pin pair" but Luminary's reference designs clearly doesn't have that many at all. Actually, they only have a maximum of four low capacitance caps for the 3.3V power supply pins and two for the VDD25 pins. What's going on? Is Luminary cheaping out on the decoupling or are they relying on the fact that they have a power and ground plane? But in that case, is the placement of the caps that are actually discrete completely arbitrary?

What am I supposed to do when I get all kinds of different messages from different sources?

[Neilm]

Deciding on the best decoupling for a device is never easy. Electronics is a very fast chaging field Rules that you learnt 10 years ago might be obsolete now - or worse may actually cause performance problems.

My recommendations is try to get some capacitors close to the pins and have bulk caps further away. I would also suggest reading this article http://www.compliance-club.com/KeithArmstrong_Article.aspx?artid=138. It gives tips on decoupling devices. You will have to register but it is free. It is interesting to note the author also recommends one cap per pin.

The capacitors should be ceramic chips as small as you can reasonably use and they should be mounted as close to the pins as possible. Also, the tracking sequance should be source - cap - chip rather than source - chip = cap. If you do the latter it does not take much track at high frequencies to render the capacitor ineffective. See the artical for tracking tips.

Yours

Neil