Schematic standard for fixed logic input?

[beaker353]

Does anyone know if there is an official standard to designate a fixed logic level on a digital logic gate/block in a schematic? Think your standard JK flip-flop where the J & K inputs are often tied high for the flip-fop to act as a frequency divider. In a schematic you can tie the J & K inputs to Vcc, but being that it's actually a logic input and not a power input, I feel that just indicating the logic level is more straightforward and makes for a cleaner and better looking schematic. Google has proven to of little help with the only thing vaguely helpful was from a IEEE standard 91-1987 document describing how to designate a fixed OUTPUT. [See attached picture] I'm guessing I could just do the same concept for an input, but I'm curious to hear if there is a/some accepted standards that are more "tribal knowledge" in the electrical engineering world as hard documentation seems to be scarce... Thanks!

-EM

[tautech]

I feel that just indicating the logic level is more straightforward and makes for a cleaner and better looking schematic.

Depending on the schematic editor that you use, assign a VCC power port label to the VCC supply AND to the GND. Then hide the IC's power pins(VCC & GND). They should connect invisibly.
Then any pin that requires to be tied H or L, just attach the appropriate power port label to it.

That will keep schematics tidy.
At a glance it is obvious which pins are tied H or L.

[beaker353]

Tautech, what you describe is what I currently do. However, with some higher pin devices and complicated sets of some pins tied high and some low, it gets messy and not easy to follow in a hurry. In textbooks they often just have a 1 or a 0 next to an input to indicate a fixed value. Would make it easier to decipher a counter MOD number or a set of slew of device parameters (my current messy schematic). I can the use the textbook style indication, but I figured there might be something more elegant that is commonly used.

- EM


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