Hi
I have a project where I need something similar to a 3:8 (74HC138) decoder. However, I also need the outputs to be tri-statable. I'm simply attempting to avoid the the addition of an external tri-state buffer. Does something like this exist?
Thanks
I don't have my Intel book handy but I seem to recall in the days of the 8080A and 8085A Intel had such a device in the 8200 series that did exactly what you are looking for. They developed it for address decoding / sharing and was seen in systems with DMA memory access which required tri-state for the address bus.
I'm not aware of any CD4xxx or 74xx part that has that feature. But it's not clear what you want. Do you want the output enable to bring all 8 outputs out of tristate, only one of which will be low with the other 7 high, or do you want only the selected output to be active with the other 7 being tristate?
And are you really sure you need this? I think it only comes in 74LS, but the '156 has open collector outputs. Would that work for you? Maybe if you show the circuit that needs the tristate, someone might see an alternate solution.
Hi rfdes,
would the 74x538 work?
I appreciate the responses, sorry for the late reply.
I need to control 8 identical SPI devices, each with it's own select signal. However, I also need to be able to initialize all 8 simultaneously. Thus the need for a 'enable all' signal. The diagram below is what I would prefer to design. However, I am trying to eliminate the need for the 'and' gates and was hoping for something prepackaged in the decoder. I asked for the Hi-Z output version because I thought that it would be more likely to exist. I could then just use pull down resistors to implement the enable signal. [ Specified attachment is not available ]
The 74154 / 74LS154 would probably work and has 16 outputs. It has 3 Gate/CS options some active high, some active low. It doesn't tristate, all unselected outputs are high and all outputs are high when the '154 is deselected. only an enabled + selected output goes low. Do your SPI devices need a high or a low enable signal? If they require a high the a '154 won't work.
The 74154 / 74LS154 would probably work and has 16 outputs. It has 3 Gate/CS options some active high, some active low. It doesn't tristate, all unselected outputs are high and all outputs are high when the '154 is deselected. only an enabled + selected output goes low. Do your SPI devices need a high or a low enable signal? If they require a high the a '154 won't work.
Thanks for the advice. I looked at the datasheet and this part doesn't do what I would like. I need the decoder outputs to be H (SPI devices are active L) when disabled. Each SPI device would be selected individually (L) but when the Enable All signal is active, then all the decoder outputs would be forced L. All of the SPI devices would then be active simultaneously.
Thinking outside the box a little, how about using a 74HC595? It's a larger package, but is cheap and would avoid an extra IC or resistors.
So, you essentially need the 8 outputs to be selectable between ten different patterns:
H H H H H H H H (none selected)
H H H H H H H L
H H H H H H L H
H H H H H L H H
H H H H L H H H
H H H L H H H H
H H L H H H H H
H L H H H H H H
L H H H H H H H
L L L L L L L L (all selected)
What about multiple devices trying to drive MISO to different potentials when more than one device is selected? You may need to think more about the details here.
That said, I'd consider a serial to parallel latch instead, maybe 74'595 or similar like edavid above, and a dual NOR gate logic chip (perhaps a 74'2G02, or two SOT-23-6 configurable logic gates). In addition to the SPI SCLK, MOSI, and MISO pins, you'd only need a separate /CS pin for the '595. '595 DS = SPI MOSI, /MR tied high, /OE = 0 nor /CS = not /CS, STCP = /CS, and SHCP = /CS nor SCLK.
This way, when /CS is high, the latch outputs are enabled, and the data goes to the SPI device(s) selected by the latch state, and the '595 sees no changes in SHCP or STCP.
When /CS is pulled low, the latch outputs go tristate. (You might wish to use pull-up resistors on the device /CS lines, so they're not selected in this state.) The next 8 bits clocked out from MOSI in SPI mode 0 will load the '595 shift register. When the /CS goes high, the shift register is latched to the '595 output pins.
This way, you can send the same sequence to any set among the 8 devices. The only thing I'd be wary about would be the MISO line, and more than one device trying to drive it at the same time. Many '595 can handle basically whatever SPI frequencies you want to use, too.
Thinking outside the box a little, how about using a 74HC595? It's a larger package, but is cheap and would avoid an extra IC or resistors.
Hmmm... yes, maybe. I'll study this a bit and see if it makes sense in my situation.
Thanks.
Have you actually tried selecting all the SPI devices at once to initialize them? I would be surprised if that works.
Have you actually tried selecting all the SPI devices at once to initialize them? I would be surprised if that works.
Yes, it actually does initialize everything properly.
Thanks
Roehrenonkel suggested the 74x538. If you could find one it should work well.
The decoded outputs can be programmed for active high or active low or tri-state. It should be possible to have a select-all state where the 3:8 decoder is not enabled and the P (polarity) input forces the outputs to the desired level.
It appears to be obsolete however. Onsemi used to make a 74F538 and Digikey seems to confirm this. It seems to be a niche device; someone may have made something similar but with a different part number. Back in the day I would have programmed up a PAL.
Intel make a Schottky version of the 74138 called the 8205.
Cheers,
I need to control 8 identical SPI devices, each with it's own select signal. However, I also need to be able to initialize all 8 simultaneously. Thus the need for a 'enable all' signal. The diagram below is what I would prefer to design. However, I am trying to eliminate the need for the 'and' gates and was hoping for something prepackaged in the decoder. I asked for the Hi-Z output version because I thought that it would be more likely to exist. I could then just use pull down resistors to implement the enable signal.
If you are ok with resistors, you can drive one end of those with a common enable and use a HC4051/HC4351
Or you can save resistors, using any 8b out Shift register - clock in 8L for select all and clock in 1L7H for select one.
Or you can use a HC259/HCS259, in a similar way - load 8L for select all and load 1L7H for select one.
There does not seem to be an inverting version of HC259 ?