Shift Register Trick

[@rt]

Hi Guys
I have two cascaded latching shift registers (74595) with their reset, latch,
and clock inputs tied together, and the carry for the first shift register
connected to the data pin of the second. So basically a single 16 bit shift register.

I only need 8 bits, and the second chip is for a trick to save microcontroller IO pins.

Say I connect the second bit of the second chip to both of the chip’s latch pins,
and always send a leading set bit, followed by a zero, and then the byte that has to be latched.
I should be able to save the IO pin normally used for latching right?
Well only if I reset afterward so the 8 data bits don’t also latch when they are shifted out.

The next part: Say the third or fourth bit of the second chip is connected to both reset pins.
Then I should also have it auto reset by the same bit earlier used to latch,
so that I can regularly shift out and latch 8 bits with only 2 IO pins.

Of course, the real answer is “try it on a breadbord”, but does anyone conceive any issue with this?
Cheers

[obiwanjacobi]

Hehehe, that's a cool idea. 

If the clock speed of clocking in the data is not too fast for the shift reg's latch and reset inputs (which would be pretty fast), I think it should be ok.

[@rt]

I’d naturally be delaying the latch bit anyway because the latch output would also serve to tell the rest of the
project the 8 bit data is valid.... acting like a clock pin for the rest of the project.
Similarly for the reset pin. It could be delayed to make sure the reset has occurred.

[H.O]

Say I connect the second bit of the second chip to both of the chip’s latch pins,
and always send a leading set bit, followed by a zero, and then the byte that has to be latched.
I should be able to save the IO pin normally used for latching right?

Hmm, I don't think it'll work. The data you shift in won't be present on the outputs until after the data is latched and since the latch input is driven by an output on the shift register the data will never be latched.

[@rt]

Dang it
The carry output of the second shift register is though!

The reset could be a second leading bit with a zero to separate them, so first the latch is set by the carry of the second chip,
then it is set again by another leading set bit which will be present on the last bit of the second chip to do the reset.

[bktemp]

Say I connect the second bit of the second chip to both of the chip’s latch pins,
and always send a leading set bit, followed by a zero, and then the byte that has to be latched.
I should be able to save the IO pin normally used for latching right?

Hmm, I don't think it'll work. The data you shift in won't be present on the outputs until after the data is latched and since the latch input is driven by an output on the shift register the data will never be latched.

Yes, and in addition to that even if the second shift register has no latch, every 0->1 transition in the serial data will trigger the latch signal.
So it won't work.
A working solution for saving pins is using a delayed signal derived from the clock to trigger latch some time after the shift clock stops.

[@rt]

I already said the reset would happen after the latch.

Say I connect the second bit of the second chip to both of the chip’s latch pins,
and always send a leading set bit, followed by a zero, and then the byte that has to be latched.
I should be able to save the IO pin normally used for latching right?

Hmm, I don't think it'll work. The data you shift in won't be present on the outputs until after the data is latched and since the latch input is driven by an output on the shift register the data will never be latched.

Yes, and in addition to that even if the second shift register has no latch, every 0->1 transition in the serial data will trigger the latch signal.
So it won't work.
A working solution for saving pins is using a delayed signal derived from the clock to trigger latch some time after the shift clock stops.

[@rt]

Only problem I see here is that for the moment of the reset, the data could be latched for a short time also.
But if the second device was a non latching shift register, there should be an arrangement that works fine.
If the reset only resets the memory and not the latch state, then I don’t see a problem at all (but I don’t know that).

Code: [Select]

The data: 1111111100011001 ->


[bktemp]

I already said the reset would happen after the latch.

It still won't work:
If you connect RESET to a latched output, once it activates reset, the shift registers stop working, because they are held in reset. Reset only resets the shift registers, not the outputs.

Instead some simple inverters should probably do the trick:
Connect the output of the shift register via two inverters to the latch clock and via another one to reset.
The first bit shifted out needs to be 1. Then you can shift out the 7 data bits (the output of the shift register has the same value as the last bit, so the last bit can't be used).
When the output of the shift register goes high, it will trigger the latch clock after a short delay by the two inverter gates to satisfy the setup time. It will also trigger reset, resetting all shift registers and also disabling the reset automatically.

[@rt]

I think I understand, but with that approach I could control the time the output on the latches are active only
because the latches don’t get reset? Then how does it reset the latches as well?

What about anded together? What I want to happen here...

8 data bits: 11111111 are latched, then reset the memory and latch (storage register) are both cleared.
always the same sequence, but timing controlled by varying the speed of the output data.

Code: [Select]

The data: 11111111-00001101 ->


[Ian.M]

What you are looking for is http://www.romanblack.com/shift1.htm
If you are trying to do it cleanly, add Schmitt trigger input buffers between the RC networks and the '595.

[@rt]

Do you think it’s still broken?
I imagine RB’s method could be used on just the second chip in the chain, but it would be better not to have to obey particular timings.

It’s an EPROM programmer, and this is the addressing. 27C800 (1Mb) EPROM, so delays will slow down an entire read/write.
I should have used binary counters, but I didn’t have any. There could be benefits of having spare shift register outputs though.

The problem was slightly rounded off to pose the question. It’s really 3 chips, and I need 19 of 24 outputs for the addressing,
but five spare outputs should still be enough.

[bktemp]

It still does not work as expected:
As soon as you shift another value in, the reset line gets set again, because the latched output for the reset line is still set.
But it could work if you omit the AND gate and use a slightly delayed latch signal for reset: It gets autmatically reset after the data has been latched.

If you want it as fast as possible, you should simply use a dedicated latch signal. This also avoids any timing problems and makes the circuit more reliable.

[free_electron]

just use i2c ... also only 2 wires and you can connect many devices on the same 2 wires.

[Ian.M]

A SPI data frame will have at most one MOSI transition per SCLK clock cycle.  Use MOSI to 'clock' a '1' through two D type flipflops wired as a two bit shift register, with both RST inputs driven by SCLK (possibly inverted, depending on the SPI mode - you want the reset to happen when the clock goes active, not when its idle).

For your latch signal, after sending N bytes, simply toggle MOSI 0:1:0:1 to take the second Q output high.  It will go back low on the first clock pulse of the next SPI frame.