Yes, many designs do this. The most recent spec has some information on this (here:
https://d1ehax0mqsd4rz.cloudfront.net/-/media/SkyWorks/SL/documents/public/data-sheets/Si5350A-B.pdf?rev=c3b847e478ca471190beaf99be50fb8e ). See section "6.6. Applying a Reference Clock at XTAL Input".
The spec says 25/27 MHz, 1Vpp for the input, but I and many others are driving it with up to 3.3V (logic-level) inputs. I typically use a 10 MHz input and others have experimented with lower frequencies as well. I've not seen any spurious response issues with the lower frequencies, but at some point the PLL loop filter response may come into play. Keep in mind that due to the feedback dividers, a 10 MHz reference clock limits the maximum PLL frequency to 900 MHz. That's the PLL max frequency spec, but we know it can go significantly faster (typically).
One advantage of using the lower reference frequency is that it gives you increased frequency resolution (smaller step size) when setting the PLL frequency.
Do not overdrive the XTAL in pin -- it's pretty sensitive and people have killed the chip when giving it an external clock. I sell external clock adaptors for a couple of SDR radios that use the Si5351, and I include impedance control and transient suppression which has provided good protection.