SPI Digital Isolation and Driving

[aep9690]

I am working on a BMS that uses SPI to communicate.  I am designing the boards to flexible so that they can be connected together to large stacks of batteries.  I want to isolate the BMS stuff from the microcontroller stuff, to this end I am using the ISO7421 by TI.

The other issue is that I am not sure that the boards will be very close together.  I anticipate that the communication lines will need to travel up to 1ft between boards.  To mitigate this I want to use the SN74AHCT125 Bus Buffer to drive the SPI lines before the communication lines go off board.

Here is my issue, I need a way to connect the buses together after the bus buffer and the optoisolators (see the picture).  The SPI_OUT lines are the lines to the next board up, the SPI_IN lines are from the next board down, and the SDI, SDO, CSBI and SCLK lines are for the BMS chip on the current board.  I don't think I can just connect the two outputs together the way I have it because the MISO line idles high, I would need something between them so that they don't short when there is a different signal.  The solution that occurs to me is to use an AND gate.  That way when one of the two MISO line idles high and the other one goes low there won't be a problem, but I am worried that this will slow down the system and cause problems.

What are peoples thoughts on this?  Am I making this too complicated or is this a legitimate problem?  If it is a problem will my solution work or is there a better way?


Thanks

[aep9690]

I should clarify that the SPI bus in this application is kind of special because instead of each chip having its own CS pin, the ICs each ahve their own address.  So the CS pin is pulled low and then the devices address is sent out followed by a command.  Its like a weird combination of I2C and SPI.

[fcb]

What CLK speed are you planning on using? What is your largest chain length? Can you chain the MISO/MOSI with you chip or does each need it's own CS line?

If you can keep the speed down, then I would use low cost opto-couplers (4N25/VOM617 etc...).

[aep9690]

The clock speed is only 250kbps.  The largest chain length possible is about 16 boards, but realistically it won't get over 13.  There is only 1 CS line total, the slave selection is done by sending a device address.

[kony]

Use schmitt buffers on input of each board for noise immunity, little logic is sutiable for that - small, cheap, much easier layout.
Having logic level defined by pull-up/down, when external board is disconected is good idea too.
No decoupling on that isolator and buffers ?
Also, I strongly discourage you from using SDI/SCL/SDO net names in shematics - I have seen too many people got burned by that (re-spinning PCBs, or modifying cable harnesses is not what you want, really).

[casinada]

As suggested you can use the TI solutions or the Analog Devices solutions: http://www.analog.com/en/interface-isolation/digital-isolators/products/index.html , or regular optocouplers but in the last case, you have to make sure you have good signal integrity at those speeds probably using optocouplers with Schmitt trigger outputs.
If you use isolation, how do you power both sides? they should be isolated from each other as well. you can power the isolated side from the tested batteries, a separate battery or an isolated DC to DC converter.

[aep9690]

I am going to include an isolated 5V power supply on each board powered from the battery. 

So I should replace the buffer I am using with schmitt buffer like this:  http://www.diodes.com/datasheets/74AHC125.pdf?  Or should I use the optocoupler with the output being fed into the schmitt buffer?  Or both?

And how do I combine the two MISO lines?  As I said before they idle high so I can't use a resistive or method.  From what is suggested I should use the method I attached.

[Bored@Work]

Max. 16 boards, max. 1 ft between boards? I would look for another bus system

[aep9690]

Can't the BMS chip uses SPI.