David's answer is correct. Also look at some other parameters.
Top FET is 1/2 the price, and 2 are used in that location.
RDS-on is a bit less than 2x the lower FET, so effective resistance will be lower for the two top FETs, and each will handle 1/2 the current, ideally, so switching losses will be reduced.
Upper FET is <1/2 the capacitance of the lower FET, so switching losses will be reduced as well using 2x in the upper location as opposed to one of the lower FET types.
Net results is better efficiency in this setup.
Lower FET will conduct about 95% of the time. Went with a more costly lower RDS-on FET in that location. Could parallel FETs for better efficiency, but it would cost more.
These are the trade-offs they chose.
I've done similar designs recently.
- LTC3891EFE based 24V to 12V converter @ 10A output. Used a single upper and lower FET since duty-cycle will be 50%.
- LTC3892EFE based 24V to 20V converter @ 20A output. Used dual upper and a single lower FET since duty-cycle will be 83%. This setup resulted in more optimal efficiency.