But how many people are still doing design with external address buses?
Heh, heh, you'll be surprised!
One of the major departments at my company is specialized on very specific reliability testing of components. Basically, we interface the Device Under Test to an internally designed tester that has a large FPGA (both in size but also on I/Os - hundreds of them). There is a DUT-specific board that ensures the electrical set-up for the DUT.
The FPGA implements an interface for the DUT to be happy and to work correctly.
The tester also have a standardized interface (up to 160 signals) to the LA to map the signals we need.
The DUT can be anything: SRAMs, DRAMs, FPGAs, TCAMs, CPUs, quite advanced devices really and sometimes even dedicated test vehicles or engineering samples. The tester copies the most interesting signals of the DUT to the LA to give us some visibility on what's happening there. That includes address/data, various buses, etc. Very useful.
We work with the component suppliers very early in the production (before release). The datasheet may not exist yet or not quite really fits the reality. Thus, in our case, a competent LA is a must.
Now, since we had tested hundreds of fairly complex devices until now, it looks like there is quite a lot of designing involving devices with a lot of interconnections. I wish those engineers all the best, since I know how things could get tough very easily.