thermal problem with asymetrical half-bridge

• thermal problem with asymetrical half-bridge
  Posted by vodka on 08 Jun, 2014 18:12
• hello,
  
  i have a mosfet(irfz46n) that it warms up when i switch on the power supply with a load inductor.
  The power supply consume 0.22 A with the current limited(tested with multimeter and  display power supply),
   this mosfet warms up a few seconds while the schottky diodes and the other mosfet is as freeze as a fish.
  So the hot mosfet and cold mosfet switch on at same time and have heatsink .
  
  Below  is my schematic and the problematic mosfet is  the left

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• #1 Reply
  Posted by Andy Watson on 08 Jun, 2014 18:37
• I would include a damping resistor in the gate of each Mosfet to ensure stability.  Q1 is unlikely to turn-on fully thereby dissipating more power than necessary. Q4 is upside-down. 
• #2 Reply
  Posted by T3sl4co1l on 09 Jun, 2014 00:11
• Many basic things wrong with this circuit...
  
  1. Oscillator and comparator are using really slow op-amps as comparators
  2. Supply is 12V so the 12V zener is redundant
  3. Op-amp supply is +/-15V yet gate signal is apparently intended to be +12/0V, causing U2 to drive short-circuit current (bad) into Q3/Q4 base (worse) all the time
  4. Q1 gate drive is insufficient to saturate, gate voltage must be above +12V when 'on'
  5. None of this matters anyway, because the load shown is a 0.47uF capacitor, which will charge once, and then do absolutely nothing.  Unless you meant that to be something else...
  
  Tim
• #3 Reply
  Posted by Jay_Diddy_B on 09 Jun, 2014 01:06
• Hi,
  
  The problem is with the Gate drive for Q1. The gate can only go to +12V minus Q3 vbe. The source of Q1 can only go to:
  
  +12V minus Q3 vbe minus Q1 Vgs
  
  So the power lost in Q1 is equal to I drain x (Vgs + Vbe)
  
  look at this post: https://www.eevblog.com/forum/projects/inductor-saturation-tester-alternative-route-to-dump-the-excess-energy/msg181720/#msg181720
  
  I use a P Channel and an N Channel in asymmetrical bridge.
  
  Regards,
  
  Jay_Diddy_B
  
• #4 Reply
  Posted by vodka on 10 Jun, 2014 05:05
• T3sl4co1l
  
  why is not saturate the gate ? when the datasheet says that the voltage gate is among -20 and + 20 V
  
  Jay_Diddy_B
  
  why is the reason for using the channel p and not channel n?
  
  
• #5 Reply
  Posted by Dago on 10 Jun, 2014 06:08
• Quote from: vodka on 10 Jun, 2014 05:05

  why is the reason for using the channel p and not channel n?

  
  Because then he'd need a floating or isolated gate drive. Remember gate voltage is referenced to source and for the upper FETs the source is not connected to ground.