Tri-state buffer part needed

[muris]

Hello,

I am designing a circuit that requires 14 tri-state buffers. They could be controlled (enabled) in pairs or independently. All parts (having >4 gates) that I looked for are controlled (enabled) in 6 or 8 gates at the same time (with one ENABLE line) which does not suit my needs. I need them independently controlled (or in pairs max).

Currently I am using 74HC125D but it has only 4 gates, meaning I need 4 chips on board which is a bit too much - I am trying to scale down the size of device.

If there exists a tri-state buffer who's gates can be enabled/disabled via I2C - that's also a good option! Buffer could be inverting or non-inverting, I can handle that in firmware.

Thanks,
Muris

[Alex Eisenhut]

What are you after? The hi-z function? A nice crappy analog switch might work if you don't really need buffering.

MC4066, MC4051 etc

Depends on the speed but you mentioned a 74HC so you're not in the GHz here.

[RoGeorge]

Might be smaller and cheaper to use a CPLD or a FPGA.

See if any mentioned here are of any help for your design:
https://www.eevblog.com/forum/fpga/a-5v-cpld-in-2023/

[muris]

Yep, it needs to have hi-z option. I am using it as a multiplexer.

Voltage is 3.3V
Max speed 32 MHz

I already have an IC with 4 gates, but need an equivalent to 74HC125D with more gates to reduce chip count on PCB.

[muris]

FPGA might be an overkill for this one? That is my first thought, but will look into it.

Anyway, still looking for a suitable equivalent to 74HC125D with more than 4 gates.

Thanks

[muris]

Not sure, but I am looking for options.

That is why I mentioned an I2C option. An octal mux or tri-state buffer which is controllable via I2C would work, I would need 2 of those on board.

I will look into multiplexers to see whats offering.

My requirement for this tri-state buffer is because I need to multiplex 4 devices onto an SPI bus, but those devices do not have EN lines. So I nees to disconnect and connect them onto the bus. There are other small things in there but that is basically it.

[Benta]

Seems to be a space constraint.
Look at the 74LVC2G125 insteed. You'll need seven of them, but they're really small.

[Benta]

My requirement for this tri-state buffer is because I need to multiplex 4 devices onto an SPI bus, but those devices do not have EN lines. So I nees to disconnect and connect them onto the bus. There are other small things in there but that is basically it.

That makes no sense.
Please sketch what you're trying to do.

[muris]

Hm, very good idea. It would actually help in PCB routing, to scatter them where they are actually required instead routing all/many to a single chip. Looks very small too.

Thanks for the tip!

[muris]

Will do in the morning, time to sleep now where I live :-)

[shapirus]

Why 14 buffers btw? (MOSI+MISO+CLK)*4 = 12 lines to start with. Then again, unless I'm wrong, you don't need to buffer CLK (you don't care if it is sent to devices whose MOSI and MISO are in hi-Z state anyway), which leaves only 8 lines to buffer/multiplex.

[shapirus]

If switching between 4*(MOSI+MISO) lines can solve the problem, then take a look at CD4052B:



Make sure to check the AC performance datasheet section though. It should be ok for up to a few MHz, but I'm not sure what frequency your SPI devices work at.

[drvtech]

Is a 74hct244 any good? Works like 2 '125s in a 20 pin package with an enable for each group of 4 buffers

[DavidAlfa]

MISO is often tri-stated when the slave is not transmitting data, so they might be joined together, unbuffered, only switching SCK and MOSI.
What are those strange SPI devices without CS?

[muris]

Thanks everyone for your inputs. I am posting now just to give a bit of a closure to this topic.

In the end I decided to use CPLD for this purpose (even though I never used them before). Xilinx CoolRunner XC2C32A to be exact. Don't remember why I have chosen this one (probably availability and pin count), but my "program" fits nicely on this CPLD and it all works as expected. Instead of having multiple chips on my board now I have just one QFN chip which is cool.

The reason for all this is that I have multiple masters on the device and multiple slaves - but just one bus which is not a true SPI bus (no CS line to disable masters), so I needed to make different "connections" between all these devices on board to support my requirements. The selection of multiplexing is done by a microcontroller which is currently on a different board. This was all just a proof of concept anyway.

Since there is also a clock on board, I use CPLD and a bit of logic inside to divide that clock signal by 2 when I need to, which is a plus.