UC3842 Boost Converter Problem

[erdemtr55]

Hi Guys,
I am a new one in here.I wanted to make boost converter with uc3842.
I reached same circuit and made one thing, but I have a problem that is not stable and not logical.
I adjusted tirmpot  2.5v in out of voltage 48v but converter boosted 80v++.
The circuit diagram and circuit traces are below.
How I solve it?

[Emo]

Hi,

What is the value of the zener connected to the trimmer pot?
If it is saturating it will block the feedback and thus not regulate

Eric

[moffy]

1. It needs to be tested with a load.
2. C3 is way too large reduce it to 470p.

[jwet]

Need a substantial input bypass on the order of the output filter cap.  Try 470 uF near the inductor 12v and .1 ufd X7R near the UC3842 16v Rail- keep them tight in both cases (short leads, minimize current loops).  Remove the zener on the outrput divider, this is not desirable- if this conducts it will tell the boost to keep going, may be a primary cause of your symptom but you need bypassing.  If you're concerned about overvoltage, there are better ways do it that we can discuss.

[xavier60]

There should be a 10K resistor between RV1 and the FB pin.
For compensation, start with 10K in series with 10nF between FB and COMP. Leave the 220pF in place.
C3 is typically 1nF.

[Konkedout]

I have built many boost converters.  I will not get too much into the component values...but:
1) Good pcb layout is essential, and (if I understand correctly) you have a single sided board with no ground plane.   You MIGHT be able to get this to work but I doubt that it can work well.  The problem is parasitic inductance in the pcb layout.   Even with a great schematic design, the parasitic inductance will cause big voltage spikes and ringing when the FET turns off and the diodes turn on.
2) Most essential is the high dI/dt AC current loop from ground, through R3 -> Q1 -> D1 & D2 (Why two diodes?) -> C5 back to ground.   You should arrange these components in the tightest possible current loop including ground from C5 back to R3.  If R3 is axial standing on end (??) that is also significant added parasitic inductance.  Much better off with something like a 1206 chip if it can take the power dissipation.
3) I mention C5 and not C4 because C5 can be a chip capacitor (I do not know what is your Vout and voltage rating).....but how about Maximum capacitance at C5 with suitable voltage rating in an 0805 chip?  The electrolytic capacitor C4 will have more parasitic inductance so I am a bit less worried about the location of that.
4) Two identical diodes at D1 and D2 is probably a bad idea.  If one gets more current it will heat more, forward voltage drop will reduce, and it will hog current.  I have done something particular with a smaller 60V schottky (less ESL but higher Vf to clip the initial rising edge) and larger 40V schottky (lower Vf but more ESL to handle most of the current).  I had opposite current rotation directions so the fields might cancel a bit.
5) In case you do not HAVE a ground plane, I have attached one here.   

[D2236]

What will be the min and max load current it needs to deliver?

[xavier60]

The spiking and ringing that will appear along the "GND" track will all be injected into the FB pin.
This could have been minimized by placing and grounding RV1 close the U2's GND pin.

[erdemtr55]

 Ok,I know you.
10nf to 1nf cap.
trimpot 3296 2kmohm.upside resistors totally 21kohm.
I adjusted trrimpot is 1120R.
Max out voltage 60v ,but I want to be 48v 100w out.
Vin 12v dc .Inductor is ee25 ferrite core and 12.5uH.
Max freq is 120khz

[D2236]

For that sort of power, you are going to push the duty cycle way past 50% and will need slope compensation to prevent sub harmonic oscillations. You may need to drop your current sensing resistor to a lower value like 50m.
Since you have a huge 1m cap on the output, it will drag your loop BW way down and impact your transient response. The compensation values need to be changed that you can get the extra gain to push up the loop BW. I will run some simulations and add the results a bit later. If you need operation on 12 V then use the UC3843.

[D2236]

The first set of images show your original values for comp (47 k, 220 p) and Rs (100 m). The sim start by setting the initial condition of the 1000 uF cap to 48 V to speed things up. Just before 2 ms the sim removes the 48 V IC and the regulator take over. Note how the 48 V line drops down when heavy loaded at 2 A while the error amp (U1-Comp) swing max positive to force duty cycle > 75% to try correct, but fail, due to the duty cycle limitation for peak current allowed from set val of Rs. Without the slope compensation, there will be stability issues from sub harmonic oscillation and double-pulse switching with these large duty cycles. It appears, we need to reduce Rs to allow higher peak currents through the MOSFET.

Next take a look at the gain/phase plots. Notice how low (~ 25 dB) our gain is at 10 Hz. That means suppression at typical mains frequencies (50, 60 Hz) will be poor and also affect things such as DC accuracy, load regulation, etc. The loop BW is low (~320 Hz) and this will cause slow transient response and longer recovery times (over/under shoot of output voltage) with sudden large load changes.

The next set show the performance difference with the comp values modified as well as reducing Rs. The output load current is switched between 1 A and 2 A. Looking at U1-Comp again; it shows that the opamp is comfortably within its operating limits and correcting for the load changes while hardly moving  and nowhere near hitting any level limits.
Looking at the gain/phase plots, the BW increased to around 1.4 kHz, while still having a healthy gain margin (~ 20 dB) and phase margin (~ 60 deg). The high-gain  margin should guard against stability issues due to component tolerances, heat, drift, etc. DC gain is now near 70 dB. We can push the BW higher by using 120 k for R9. This will make the BW about 1.8 kHz while still keeping the phase margin at 60 deg. Gain margin drops down to 12.5 dB, which is still very safe.

Note: The 1000 uF cap (C1) is modeled with an ESR of 50 m Ohm, and not  visible in the schematic.