Open source USB scope

[cyberfish]

Hi, new member here . Second year electrical engineering student.

Yes, I know USB scopes are complete utter garbage.

That's why I'm not going to buy one.

I'm designing one .

This is mostly for learning purposes (as with all the money I have spent/will be spending, I could've gotten a nice digital scope already).

I have been working on it for the past few weeks, and have all the parts chosen, and the schematics drawn.

It's 100Msps, and about 50MHz analog BW. Uses a Xilinx Spartan 3AN FPGA, and single version of the ADCs in those Rigol scopes, not overclocked . I'm using REAL 100Msps parts.

There are plans to make it 1Gsps in the future, using interleaved ADCs and staggered clock, but that's beyond me at the moment, so the first iteration will only have 100Msps (fastest from single ADC).

Schematics here -
http://cyberfish.wecheer.com/blog/wp-content/uploads/2010/06/scope.png

More details, including BOM, on my blog -
http://cyberfish.wecheer.com/blog/?p=441

It's very long and boring, though, and the schematic should be pretty self-explanatory.

The part I'm most unsure about is the analog front end, as we haven't done any high speed circuit design in classes yet, so most of my knowledge comes from random places on the internet. Would be great if anyone wants to take a look .

Thanks

[cyberfish]

Some explanations on the analog frontend, just so you won't need to read my blog -

Input from BNC probes go into a 1Mohm resistor in parallel with 20pF (so the probes can compensate for it). The signal is buffered by a wideband, unity-gain stable JFET op amp (OPA656), before being fed to a summer (the pre-amp of the programmable gain amplifier), that adds a bipolar offset from a DAC to the signal. Then it goes to a programmable gain amplifier, and finally the ADCs.

[EEVblog]

Schematics here -
http://cyberfish.wecheer.com/blog/wp-content/uploads/2010/06/scope.png

The problem with that front end is that there is that the input overload protection will blow very easily. Any overvoltage input is directly shorted by the diodes - bad news!
You need an input series current limiting resistor at a minimum.

Dave.

[NiHaoMike]

Perhaps, with modifications, it could be used as a digitizer card for SDR (software defined radio, GNUradio in particular)? 100Msps is very fast for a continuous capture digitizer card. The analog requirements are much simpler - 50 ohm or 75 ohm input, perhaps only a 500mVpp to 5Vpp or so input amplitude range, and much less need for overload protection.

[cyberfish]

The problem with that front end is that there is that the input overload protection will blow very easily. Any overvoltage input is directly shorted by the diodes - bad news!

That is a very good point... I must've had a brainfart .

I will split the 1Mohm and 20pF into a divider (with equivalent total impedance), and add the diodes in-between.

Will update the schematic when I get home today.

that can be quite complex! just make sure you got 1st class degree. dont fail just because u ar doing this too much.

Certainly .

I'm doing internship right now (as a software developer), so this is my evening and weekends project. Hopefully I can finish (or at least finish most of) it before school starts again in 8 months.

Perhaps, with modifications, it could be used as a digitizer card for SDR (software defined radio, GNUradio in particular)? 100Msps is very fast for a continuous capture digitizer card. The analog requirements are much simpler - 50 ohm or 75 ohm input, perhaps only a 500mVpp to 5Vpp or so input amplitude range, and much less need for overload protection.

I have never heard of it, but that sounds very interesting.

I'm not sure what you meant by continuous capture. Does that mean streaming samples? That won't work unless we make it a PCI[-E] card or something, since USB 2.0 would limit the rate to about 40Msps, 1 channel. Also, if the smallest signal is 500mVpp, AC coupled (sounds like it to me), a lot of the circuitry can be taken out - the DAC for offset, and programmable gain amplifier. I suppose it can just be an ADC with an FPGA coordinating the acquisition, and whatever interface chip to connect it to the computer.

[joelby]

Is 8-bit enough for SDR? The SDR I'm designing will be 14-bit if I can figure out how to solder the QFN chip by hand.

[NiHaoMike]

I have never heard of it, but that sounds very interesting.

I'm not sure what you meant by continuous capture. Does that mean streaming samples? That won't work unless we make it a PCI[-E] card or something, since USB 2.0 would limit the rate to about 40Msps, 1 channel. Also, if the smallest signal is 500mVpp, AC coupled (sounds like it to me), a lot of the circuitry can be taken out - the DAC for offset, and programmable gain amplifier. I suppose it can just be an ADC with an FPGA coordinating the acquisition, and whatever interface chip to connect it to the computer.

Continuous capture means the ADC is constantly sampling at the rate you desire and send every sample to the host system. Unlike an oscilloscope that only sends parts of acquisitions to the host system.

USB 3.0 is good for something like 3.2Gbps.

Is 8-bit enough for SDR? The SDR I'm designing will be 14-bit if I can figure out how to solder the QFN chip by hand.

My old Dell HDTV card (~9 years old, came in a used Dell GX110) has only an 8 bit ADC. It worked nicely back in the days, but can't even come close to the modern cards that use 10 bits or more. What's interesting about it is that the decoder chip (Micron) appears to be a general purpose DSP or FPGA since there's 8MB of DRAM and 512k of Flash on the board. (Too bad there's no datasheet available, or I'll reprogram it to operate as a digitizer card, complete with tuner!)

[joelby]

What's interesting about it is that the decoder chip (Micron) appears to be a general purpose DSP or FPGA since there's 8MB of DRAM and 512k of Flash on the board.

That's interesting! I briefly looked in to using cheap TV tuner cards with composite input as a high speed ADC. It should be possible by fiddling with the Linux drivers, and inserting TV-esque signal pulses to fool the tuner chip (maybe!)

With regards to data transfer, I suppose that the normal way to get around this is to consider that you don't actually care about the complete signal unless you're doing data acquisition, so you can decimate it before transferring it to the host computer at a leisurely rate. Alternatively, buffer and transmit the whole lot in conjunction with a run/stop mechanism. Or compress the data!

[NiHaoMike]

That's interesting! I briefly looked in to using cheap TV tuner cards with composite input as a high speed ADC. It should be possible by fiddling with the Linux drivers, and inserting TV-esque signal pulses to fool the tuner chip (maybe!)

The design varies a lot. In virtually all modern designs, the ADC is integrated into the decoder DSP. (Also note that Auvitek uses 12 bit ADCs.)
http://www.auvitek.com/Products/AU8524.html
However, some designs allow the DSP part to be bypassed.
http://www.auvitek.com/Products/AU8515.html
That is sometimes done for cards that can receive FM. FM decoding in software is very easy (basically a frequency counter) and does not take much in the way of resources, so it makes more sense to do the decoding on the host system instead of dedicating logic or firmware to that task.

[cyberfish]

Updated schematic with voltage divider added in.

http://cyberfish.wecheer.com/blog/wp-content/uploads/2010/06/scope.png

Any more suggestions?

I'm worried about the capacitance of the diodes and their effect on the circuit. Need to look into that some more...

[cyberfish]

Is 8-bit enough for SDR? The SDR I'm designing will be 14-bit if I can figure out how to solder the QFN chip by hand.

Have you seen SparkFun's skillet reflow soldering tutorial?
http://www.sparkfun.com/commerce/tutorial_info.php?tutorials_id=59

I think I'm going to try it for this project. Or maybe toaster oven. Skillet (hot plate) certainly sounds easier.

[joelby]

Have you seen SparkFun's skillet reflow soldering tutorial?

I have! The need to have someone else cut a stencil makes it unappealing for one-offs. You can buy pre-made stencils for QFN parts, but even those are very expensive. I'll try my luck with Kapton tape and drag soldering

[cyberfish]

Eh? Am I missing something?

I thought it's just apply paste, then place the chip by hand (or tweezer), and put the whole PCB on a skillet (powered frying pan), turn it on, and stare.

[charliex]

in the apply paste part they use a stencil to make sure it goes to the right places.

You can do it by hand with a dispensing needle but its hard work getting the consistencies right. I've done brass stencils on my cnc and had laser cut ones from polulu the thing i didn't like about the laser cut was the edges made it trickier to do the paste with a scraper. The brass ones work a lot better but you need a cnc.

reflowing with a hotplate is a lot easier than it would seem, i tried a few different things, and i found that use less paste than seems right, leaded paste, and it works great. the pieces don't snap into it place as easily as some tutorials suggest, but they will move a little bit.

the profile is important, you want to ramp up slowly enough to not dry out the paste, or warp the board.

i tried it with unleaded and a target hotpalte, and it just would barely get to the temperature needed to melt the paste, and the board discoloured (around 225F ) with the leaded paste I can get by with around 193F which is just borderline for the batchpcb boards to begin to discolour.


for a tqfp i just used as little as paste as i could, then used copper braid to carefully remove the bridges, but you have to be careful since the copper braid really sucks up the solder fast, so you can end up remvoing too much.

[cyberfish]

Ah I see. Sorry for the late reply. I thought I set up email notification on this thread... apparently not.

Very good advices!

I am probably going to do skillet reflow for this project. Did some experimenting with my skillet to try to match the JEDEC recommended reflow profile. The heating part is pretty easy. I can match the profile pretty closely. Cooling is a problem, though. JEDEC says tliquid (time above liquidation temperature, 185C) should be 60s to 120s, with a peak of 225C minimum.

It takes my skillet something like 5 minutes to cool down from 225C to 185C. Not sure what I'll do yet. Maybe I will only go to 200C or something.

By the way, I'm assuming your temperatures are in C instead of F? They sound very low for F.

[cyberfish]

And I've done the layout for my project!

http://cyberfish.wecheer.com/tmp/board.png

and in gEDA's PCB format
http://cyberfish.wecheer.com/tmp/board.pcb

and here is the schematics (posted before) -
http://cyberfish.wecheer.com/blog/wp-content/uploads/2010/06/scope.png

Since this is my first board ever... I'm guessing there are glaring errors everywhere.

Probably going to get it manufactured by Olimex. I think I set up the DRC rules right...

All help appreciated.

Thanks!

[jahonen]

Well, here are some comments that come into my mind (from somewhat non-hobbyist point of view):

- Check the ADC biasing scheme
- Consider driving the ADC differentially (via fully differential amplifier, something like TI THS4130) as this usually yields to best dynamic range
- PGA will need the ground thermal pad vias, they are missing? Also, traces under the PGA create risk of short circuit for same reason, solder mask is not reliable insulator!

Others:

- Fill the top side with copper too and place stitching vias between top and bottom grounds in something like 10x10 mm grid
- Remove the thermals on non-through-hole component vias, they just make the layout worse
- Power distribution net seems somewhat flimsy considering what you are trying to do here
- Add more global decoupling capacitor everywhere on your VCC nets
- Or even better, consider seriously using multilayer PCB for mixed signal project like this, SI and analog noise issues can drive you crazy otherwise
- If you can't afford that, then use as thin PCB substrate as you possibly can, 0.8 mm thick or even less.
- Do not share ground vias, use one via per ground connection
- Try to use more SMD components, especially in the input stage

Regards,
Janne

[cyberfish]

Thanks for the great advices! Most of them make a lot of sense to me.

- Check the ADC biasing scheme
- Consider driving the ADC differentially (via fully differential amplifier, something like TI THS4130) as this usually yields to best dynamic range

Do you mean the way reference is generated? I am using the internally generated Vref (1.25V).

I just read up on differential amplifiers, and they do seem to be more suitable. For the THS4130, the datasheet says it has both differential input and output. Does that mean for the output, I can just tie the negative to ground, and positive to input of the PGA?

- PGA will need the ground thermal pad vias, they are missing? Also, traces under the PGA create risk of short circuit for same reason, solder mask is not reliable insulator!

Hmm I totally ignored the thermal pads. Will look into that. I am not sure if I can completely eliminate traces under the PGA, but I'll see what I can do. Maybe I can make sure there is only one voltage, and make the thermal pad float (the datasheet says it's electrically insulated).

The FPGA also has a similar problem, but I can't think of a way to do the power distribution without using the space under the FPGA (2 voltages with pins on all 4 sides). Maybe I can move them to the solder layer, but I'm not sure how much that will help (since the vias still need to be there). Or maybe I can just push them away from the center to clear the thermal pad area.

- Fill the top side with copper too and place stitching vias between top and bottom grounds in something like 10x10 mm grid
- Remove the thermals on non-through-hole component vias, they just make the layout worse
...
- Add more global decoupling capacitor everywhere on your VCC nets
...
- Do not share ground vias, use one via per ground connection

That make sense. Will make those changes.

- Power distribution net seems somewhat flimsy considering what you are trying to do here

Can you please elaborate on that?

- Or even better, consider seriously using multilayer PCB for mixed signal project like this, SI and analog noise issues can drive you crazy otherwise
- If you can't afford that, then use as thin PCB substrate as you possibly can, 0.8 mm thick or even less.

Multilayer PCB would be great, but since this is my first board, I'm not sure if going multilayer would be a good idea. An oscilloscope is probably not a good idea for a first board, too, but... .

Will use a thin PCB.

- Try to use more SMD components, especially in the input stage

Is there other advantages to SMD components beside board size? I used through hole components there because I thought I may have to change components there later (eg, using variable capacitor for better matching), and it's easier with through hole.

Oh and this is the first project I'm using SMD components, too .

Thanks again for your time.

Will make changes and post updated board tonight.

[joelby]

Is there other advantages to SMD components beside board size? I used through hole components there because I thought I may have to change components there later (eg, using variable capacitor for better matching), and it's easier with through hole.

Parasitic effects (unwanted capacitance and inductance) are reduced because of the shorter leads.

I'm working on something broadly similar that may either help or hinder you - a four-channel SDR - and have used a differential amplifier. Note that I have no idea if this configuration will work and would greatly appreciate any input from Janne and the other forum gurus before I build it

The input here is baseband RF (containing CW signals from about 50KHz to 5 MHz) of around -80 dBm and above. The preceding circuit down-converts using two Mini Circuits ADE-1LH+ diode mixers and some filters. Here I've used the AD8351 to convert the single-ended output of the mixer to differential and to provide some gain. VCM sets the common mode voltage of the amplifier and the ADC to 1/2 VDD. Is this a broadly sensible arrangement?



Addendum: after looking at the THS4130 data sheet, I realised that the LTC2171's VCM12 is actually a VDD/2 output reference! Please ignore the resistor divider arrangement and consider VCM12 to be connected directly to the amplifier's VOCM (and bypassed to ground).

[jahonen]

- Check the ADC biasing scheme
- Consider driving the ADC differentially (via fully differential amplifier, something like TI THS4130) as this usually yields to best dynamic range

Do you mean the way reference is generated? I am using the internally generated Vref (1.25V).
I just read up on differential amplifiers, and they do seem to be more suitable. For the THS4130, the datasheet says it has both differential input and output. Does that mean for the output, I can just tie the negative to ground, and positive to input of the PGA?

No, I mean that ADC inputs should be at some common mode voltage. If I understood the PGA datasheet correctly, it does not provide any kind of biasing.

Imagine that you have let's say, 1 volt differential signal, and the ADC is powered from 3.3 volts. If the common mode voltage would be 0 volts, then your positive input to the ADC would be at +0.5 volts and negative input would be at -0.5 volts. Now since ADC supplies are at 0 and 3.3 volts, the input common mode range would be violated. But if you rise the common mode to 1.65 volts, then you would have positive input at 2.15 volts and negative input at 1.15 volts. That would be perfectly acceptable. The differential amplifier will make this biasing easy using the Vocm pin, which is just tied to desired common mode voltage.However, AD9283 seems to be a bit tricky in this respect, it wants to bias the inputs by itself. However, it is mentioned in the datasheet that optimum common mode voltage would be around 0.3x analog supply voltage, or 1 volt when using 3 volt analog supply voltage.

- PGA will need the ground thermal pad vias, they are missing? Also, traces under the PGA create risk of short circuit for same reason, solder mask is not reliable insulator!

Hmm I totally ignored the thermal pads. Will look into that. I am not sure if I can completely eliminate traces under the PGA, but I'll see what I can do. Maybe I can make sure there is only one voltage, and make the thermal pad float (the datasheet says it's electrically insulated).

The FPGA also has a similar problem, but I can't think of a way to do the power distribution without using the space under the FPGA (2 voltages with pins on all 4 sides). Maybe I can move them to the solder layer, but I'm not sure how much that will help (since the vias still need to be there). Or maybe I can just push them away from the center to clear the thermal pad area.

This is one of the reasons I recommended the multilayer board, with basic 4 layer board you can dedicate the 2nd layer to contiguous ground plane and 3rd layer to power plane, and still you have two good routing layers. I don't know if it is wise to leave the thermal pad unconnected, would the heat become an issue, at least with PGA?

- Power distribution net seems somewhat flimsy considering what you are trying to do here

Can you please elaborate on that?

I meant that the power distribution is build from relatively narrow traces, instead of the plane, see above.

- Try to use more SMD components, especially in the input stage

Is there other advantages to SMD components beside board size? I used through hole components there because I thought I may have to change components there later (eg, using variable capacitor for better matching), and it's easier with through hole.

Oh and this is the first project I'm using SMD components, too .

Thanks again for your time.

Will make changes and post updated board tonight.

Like already said, SMD components have less inductance, or generally smaller parasitics. Even among those, smaller components are usually better in that respect. BTW, I think that SMD capacitors and resistors are much easier to change using two soldering irons, than through-hole ones, especially on multilayer or even through-plated boards.

Regards,
Janne

[jahonen]

I'm working on something broadly similar that may either help or hinder you - a four-channel SDR - and have used a differential amplifier. Note that I have no idea if this configuration will work and would greatly appreciate any input from Janne and the other forum gurus before I build it

I have no experience on these particular chips, but schematic looks pretty much okay except the mentioned Vocm-connection.

Regards,
Janne

[cyberfish]

No, I mean that ADC inputs should be at some common mode voltage. If I understood the PGA datasheet correctly, it does not provide any kind of biasing.

Imagine that you have let's say, 1 volt differential signal, and the ADC is powered from 3.3 volts. If the common mode voltage would be 0 volts, then your positive input to the ADC would be at +0.5 volts and negative input would be at -0.5 volts. Now since ADC supplies are at 0 and 3.3 volts, the input common mode range would be violated. But if you rise the common mode to 1.65 volts, then you would have positive input at 2.15 volts and negative input at 1.15 volts. That would be perfectly acceptable. The differential amplifier will make this biasing easy using the Vocm pin, which is just tied to desired common mode voltage.However, AD9283 seems to be a bit tricky in this respect, it wants to bias the inputs by itself. However, it is mentioned in the datasheet that optimum common mode voltage would be around 0.3x analog supply voltage, or 1 volt when using 3 volt analog supply voltage.

Ah I see. Thanks for the great explanations. The PGA is single ended, so I was thinking of biasing it with the "offset" input (from the DAC), which gets added to the signal.

I spent a few hours reading up on differential amplifiers, but I think I will stick with single-ended for this one, since I am not familiar with them yet, and the selection for high speed differential PGAs is very limited (I could only find one - TI PGA870). Maybe I will switch to differential for the next version or something. There are many things I want to add/change eventually. Like staggered clocks to get 1Gsps, and true AC coupling. Maybe even replace the PGA with a bunch of fixed gain amplifiers and a multiplexer.

This is one of the reasons I recommended the multilayer board, with basic 4 layer board you can dedicate the 2nd layer to contiguous ground plane and 3rd layer to power plane, and still you have two good routing layers. I don't know if it is wise to leave the thermal pad unconnected, would the heat become an issue, at least with PGA?

That would certainly make things easier. I think it would be a little too expensive, though. My board is ~3" by 6". With BatchPCB it comes to $144 for 4 layers.

Another problem is the large number of supply voltages on this board. I have 5V/-5V for amplifiers, 3.3V for ADC/DAC, and 1.2V for FPGA.

I am not sure if the heat will be a problem, but I think with some work, I can clear the traces under the PGA, and give it a proper thermal pad.

I am more worried about the FPGA, though, since I don't see how the power "rings" can go outside the FPGA footprint.

I meant that the power distribution is build from relatively narrow traces, instead of the plane, see above.

I think I can give them thicker traces. But of course, it's never going to be as good as a plane.

Like already said, SMD components have less inductance, or generally smaller parasitics. Even among those, smaller components are usually better in that respect. BTW, I think that SMD capacitors and resistors are much easier to change using two soldering irons, than through-hole ones, especially on multilayer or even through-plated boards.

That sounds good. Will change them to SMD components.

Sorry the changes turned out to be more involved than I thought. Will do them this weekend.

[joelby]

Thanks Janne, I'll run off a board and let everyone know if it works!

[cyberfish]

Updated -
http://cyberfish.wecheer.com/tmp/board-1.png
http://cyberfish.wecheer.com/tmp/board-2.png

Changes -
- copper pour on component side. Saved lots of vias, too
- SMD components in the frontend
- thicker power traces (40 mil vs 25 mil)
- no more thermals on vias
- no traces under PGA (thermal pad added, too). Turns out FPGA is fine, since the one I'm getting doesn't have a thermal pad
- global decoupling caps, especially on the left side, for the analog chips

Thanks again for the great advices!

Any more?