uP + DDS Chip Exist ?

[richsf]

Is there a higher performance (50MHz range)  DDS that has an integrated programmable micro-controller on the same chip ?

[jwet]

Not that I've seen at 50 Mhz.  I've seen things that might get you to 20 Mhz or so.  Here's what I think I know-

1. Several processors have fancy timers in them that border on DDS.  They have a timer with a programmable auto reload and you could feed overflows to a pin.  The original propeller had a timer mode like this that would give you something like DDS but the frequencies weren't up to 50 Mhz.  I did an HF software defined radio and used the propeller for the user interface and the LO- it worked up to 20 or so Mhz but there are better ways.

2. There are a lot of FPGA's that have uP's embedded and a DDS (less the DAC) is a pretty standard VHDL design- it doesn't take a ton of logic.  There are some fancy DSP types of things that go in real DDS chip that suppress spurs, etc.  ADI has tradenames and patents for "spur killer" algorithms.  I know my propeller DDS had some funky spurs that I never ran down.  Some FPGA's have softcores and some have hard cores.  Someone (Triad IIRC) makes an FPGA with an ARM M0 hard core  embedded which is a nice little processor for housekeeping and a graphic UI. 

3. You can use a pretty moderate FPGA and an off the shelf uP.  This is probably most cost effective.  The <$100 2 Channel ARB signal generators do it this way.  They often also make the DAC with a big pile of resistors in an R-2R for format.

4.  Using a standard ADI DDS and a standard CPU of some kind is easiest.  I built quite a few DDS local oscillators with AD9852 and a little Atmel 89C2051.  It drove an LCD module, had a quadrature input and a few buttons.  Might use an AVR or little Arm these days but was trying to make it small.

5. I don't know your requirments but the 5351 clock generator is technically a PLL but is clever and can do a lot of what a DDS will do except stuff like fast FSK, etc.

[PCB.Wiz]

Is there a higher performance (50MHz range)  DDS that has an integrated programmable micro-controller on the same chip ?

Analog Devices would be likely to have done that, if there was customer demand.

Which details of DDS do you need?  What output waveform / frequencies / steps do you need? 

The Parallax Prop 2 has some elements of DDS, and multiple cores.
Some PIC parts have NCOs.

5. I don't know your requirments but the 5351 clock generator is technically a PLL but is clever and can do a lot of what a DDS will do except stuff like fast FSK, etc.

Yes, the Si5351 / MS5351 are low cost PLLs with Xtal/External Osc.
There are also new parts from TI like LMK3H0102 & LMK3C0105 that are i2c and integrate a 2.467 GHz BAW Oscillator to synth 2.5~200MHz outputs.

Skyworks (nee Silabs)  also have i2c controlled Clock parts with VCOs of ~ 5GHz and up to ~ 13GHz
https://www.skyworksinc.com/en/Products/Timing-Oscillators

[richsf]

Thanks guys, you definitely brought up some things I wasn't aware of for future consideration, but I think a separate micro controller is the best way for me to go.  So far just a 'thinking about something' project. 

[spostma]

Maybe you could reuse an old technique making a stepped sinus using johnson ring counters
https://www.ti.com/lit/pdf/SBOA550

the PIO peripheral of a rp2040 or RP2350 probably could generate the digital Johnson ring counter signals at 6x or 8x the 50MHz sinus frequency.

[Doctorandus_P]

There are a bunch of projects on github for DDS based function generators for STM32. Every now and then I'm thinking about doing something with one of those projects, and possibly improve it. The goal would be to do (very slow) DDS "sample sorting" in software, to generate a buffer, and then send that buffer to the DAC via DMA. When the settings change (wave form, amplitude, frequency) the uC first calculates a new buffer, and then modifies the DMA to use that new buffer (ideally near a zero crossing, so output disruption is minimal) Most of the software for this is pretty straight forward. The only doubt I have is wraparound for the DMA buffer. I think newer STM32 chips can wraparound DMA seamlessly, but older variants would have a timing gap. If such a gap has a fixed width, it can be partially compensated for in software.

But overall, if you want / need performance, put the whole thing (possibly including the uC) into an FPGA.

[NiHaoMike]

Maybe you could reuse an old technique making a stepped sinus using johnson ring counters
https://www.ti.com/lit/pdf/SBOA550

the PIO peripheral of a rp2040 or RP2350 probably could generate the digital Johnson ring counter signals at 6x or 8x the 50MHz sinus frequency.

RP2350 also has "HSTX" which is even faster.