Verifying a controller memory map

[metertech58761]

So, I'm getting ready to wind down a documentation project after tracking down most of the boards for a semiconductor wafer processing system I used to service years ago.

One of the remaining loose ends is working out the memory map of the main controller in order to properly analyze the code dumped from the EPROM on the CPU board.

If this was based on the 6800 family of MPUs (or even the trusty 6502), I would be able to pick out the addresses in the code, but this particular controller uses a pair of 8085s, and I still haven't had the time to get my mind around the intricacies of Intel assembly code.

What does the IO/_M line (and its reciprocal, _IO/M) do?

Anyway, here are the schematics I've worked out - and I just want to confirm my understanding of the address for each of these boards (upper 8 address lines only):

These three boards all have the address hard-wired:

290014 (Display): 1111 111x (FE)
290055 (Comm): 1100 000x (C0)
290077 (8253 timer): 1111 10xx (F8)
290077 (RAM): 1110 0xxx (E0)

These two, however, have the address selectable via DIP switch:

290017 (I/O): 0000 00xx (00) But doesn't that conflict with the ROM space at 0000-3FFF?
290020 (I/F): 1010 00xx (50)

I've also attached the 'source dump' if it helps...

[moffy]

"These two, however, have the address selectable via DIP switch:

290017 (I/O): 0000 00xx (00) But doesn't that conflict with the ROM space at 0000-3FFF?
290020 (I/F): 1010 00xx (50)"

The 8085 can have seperate 16 bit memory and adress spaces, the IO/M signal, hence the aparent overlap: https://www.tutorialspoint.com/memory-mapped-i-o-in-8085-microprocessor