I have a project that will have tens of amps flow through it. It is just a switching circuit with no signals that need to keep their integrity. I plan on halving the required trace width but mirroring it on both sides of the PCB and via stitching the traces. In my mind this will allow for better heat transfer and therefore the two traces will act as one and the current will safely be handled. Right now I'm using a 5mm grid pattern which I believe is overkill, but I'm not bothered by that.
Is this a via-ble (hehe) strategy? Are smaller vias better here so that more copper stays on the traces?
Via stitching for current sharing likely wont buy you much in the application you are describing. Your mirrored traces can be thought of as distributed resistors and there will be a voltage drop across their length. However they are identical resistors so the voltage at any given point will be the same, since the voltage is the same at every point you no current will flow through the via. however the hole used for the via does cut down on the cross sectional area of your trace making it a higher resistance than it would be otherwise. So the via stitching will likely make things worse, unless it is a copper filled via $$. All this is assuming ideal dimensions and materials. In reality one trace will take more current than the other however it will be minimal since the more current it caries the hotter it will get causing the resistance to increase transferring more load to the other trace.
Normally I do stitching when I have uneven loads or ground planes on multiple layers and want to minimize current loops or I am moving high current trace from one layer to another.
Understood. Those were all things I was thinking, but couldn't articulate them. I am looking at it from a heat spread point of view. By stitching the vias together, the spread of heat can occur more evenly and the likelihood of hot spots will be minimized, right? This will then slow the overall heating of the traces make them act more as one cohesive trace. The max current may be reduced, but the stitched, mirrored traces would offer a better path than non-stitched, mirrored traces, right?
On another note, will thermal relief spokes on PTH pads decrease the current capacity (ie: burn up before the trace)? I don't think it will since the length of the spokes is so small that the resistance of them (and therefore the voltage dropped) is quite a bit lower than the rest of the trace.
Since the traces are the same they should heat at more or less the same rate, heat flux is the same as a voltage potential is to locations are at the same temperature no heat will flow. via stitching is only really useful if you want to to flow a lot of current or wants really low impedance between to layers. your application I think would be harmed more than helped
That being said if you are that concerned with hot spots going to wider trace or heaver copper would probably or keep the solder mask off parts of the trace and build it up with solder, be the right way to go. I use this tool all the time for basic sanity check and usually design things with lots of margin.
http://www.4pcb.com/trace-width-calculator.html You are right about the reliefs, also in addition to the minimal power, the relief can use the connected trace and pad as a heat-sink letting a higher current safely flow through than a trace of the same width.
Also in all this I am assuming a steady state current and not a pulsed current. Pulse handing is a whole other class of fun.
Another note I din't answer the question you actually asked. Sorry. A larger number of small vias is generally more efficient at moving current/heat between layers than a small number of larger vias. These of course being standard non-filed vias. Copper filled vias get around this problem but it is an expensive step mainly used in military and aerospace applications.
You will have a slight advantage from stitching, but probably not why you'd expect.
First of all, if the top and bottom copper is carrying equal current, then heating will be equal, period. That's a simple setup, and if your situations fits, then the following will apply.
Trace temperature rise is limited by heat loss. Ultimately, the only heat loss is convection (or radiation or conduction) off the board surface. If the board is in free, still air, then it's around 150 in^2*C/W (yes, a horrible bastard of a unit, I know) for all surface area.
If you have a single trace (well, in this case, one on each side, but in the same location), and nothing else on the board, you get heat dissipation from the area of the trace itself... but also, the heat spreads laterally a modest distance, and the board itself helps out with heat dissipation.
Now here's the kicker. PCB is more conductive laterally (in-plane) than depthwise (through-plane). If you just have trace on the surface, only the surface of the PCB carries heat sideways. The core, even right in the middle, may be cooler than the traces, because the core layers conduct a farther distance.
Now, if you stitch this construction with vias, you have quite a bit more through-plane conductivity. This carries heat to the core, and the heat spreads a somewhat larger distance, reducing temperatures overall.
It's more pronounced with inner copper layers, which can be pierced (or joined) with vias, and carry even more heat sideways than the laminate itself.
Of course, the advantage also goes away if you are using the whole board to carry current. That is, if the whole board is getting hot, there's no spot that's cooler, for heat to spread out into. The temperature is largely similar to the expected case, based on copper resistivity, and PCB dissipation capacity.
Tim
Hmm. Interesting point. I think some real-life tests need to be done. Thanks for your insight.
Can you add solder mask opening and solder paste opening on the traces, (at least partially) filling the vias with solder? Or manually drag solder the traces, filling the vias? It would take a few seconds to do manually.
That would help with the problem caused by reducing cross-sectional area due to the holes. Of course the conductivity of solder is not as good as copper, but copper filling is usually quite expensive and not every board house do that.
With filled holes, even with just standard solder, I'd think it's a good idea to stitch a lot, for the reason T3sl4coil gave above.
Well, for this purpose, the stitching doesn't need to be much more frequent than the lateral heat spreading property of the material. I'd guess comparable to PCB thickness.
For sure, you'll have more benefit from increasing trace thickness (simply getting heavier copper, or adding solder as Siwastaja mentioned) or width.
The difference with/out vias will be in the 5, maybe 10% range, too little to care about.
Tim
I have heard a lot of arguments from both sides about the effectiveness of leaving the soldermask off and covering the traces with solder. It's time to find out for myself. I just drew up and ordered a batch of test boards. The design has three 11mm wide traces. The first trace is heavily stitched with vias. The second is lightly stitched and the third has no stitching. The traces are 90mm long and I left the soldermask off the bottom of all three. I will get testing once the boards arrive in about a week.
Didn't Dave already cover this?
The solder on the traces? Now that you mention it, yes. Yes he did.
Solder is about 5 times lower conductivity but 5 times thicker than 1oz copper, so it about doubles the current capacity, give or take. Obviously, it's not going to be an even layer, and you can't cover the whole trace either (you need some solder mask near the ends to prevent solder thieving during reflow, and some overlap over the edges of the trace probably improves strength (resistance to peeling?) and corrosion resistance), but it certainly helps enough to bother with if you need it.
Tim
Via stitching alongside the entire track does not make sense. What you can do is the following:
Put vias at the beginning and end of the high current trace, since you want to route it on multiple layers, right? So but a bunch of via there. The smaller the better, I used 0.3mm vias. I made a test PCB just to test the optimal via size (for standard 35/70um 4 layer board ), because there was a fruitless discussion at that time at the company. So put around 1 via/ 1-2 amp both ends. Tightly coupled. You should know, the only limiting factor for a trace/ piece of copper to carry current is the temperature.
Since you are dissipating the heat on both sides, you actually need less width to carry the current than half, but you know the rules for high current: better safe than sorry.
However the hole used for the via does cut down on the cross sectional area of your trace making it a higher resistance than it would be otherwise. So the via stitching will likely make things worse, unless it is a copper filled via $$.
This is an interesting topic, do you have any reference ? Intuitively I am of the same mind, but I am looking for a more scientific explaination. I am wondering if this is also true for small vias, because the copper on the via barrel could compensate the copper missed on the via holes.
However the hole used for the via does cut down on the cross sectional area of your trace making it a higher resistance than it would be otherwise. So the via stitching will likely make things worse, unless it is a copper filled via $$.
This is an interesting topic, do you have any reference ? Intuitively I am of the same mind, but I am looking for a more scientific explaination. I am wondering if this is also true for small vias, because the copper on the via barrel could compensate the copper missed on the via holes.
initial guess would be when diameter of hole is less that thickness of pcb, i.e. you lose one diameter of track width on top and bottom, and add one pcb thickness on each side of the hole
Basically that you conductivity is proportional the the cross sectional area of your condutor. If you punch a non conductive hole in it you have less copper. I'll admit there might be some combination of hole size and plating thickness that this idea doesn't hold for though.
Via stitching alongside the entire track does not make sense.
I have seen people (in professional companies) stitching every possible GND plane because "it would help against noise and EMI"
@ T3sl4co1l
Bottom bs Top, can actually make a quite significant difference.
Since the pcb itself prevent heat from convecting, bottom traces have a tendency to warm up a little bit more.
That also depends how much space there is between the PCB and the surface it's mounted on.
btw, I read "switching signal" in the start post?
What frequencies are we talking about?
Via stitching alongside the entire track does not make sense.
I have seen people (in professional companies) stitching every possible GND plane because "it would help against noise and EMI"
Stiching ground planes together around high speed signals absolutely helps with EMI and cross talk. Parallel planes that aren't stitched together aren't ground planes, they are wave guides.
Via stitching alongside the entire track does not make sense.
I have seen people (in professional companies) stitching every possible GND plane because "it would help against noise and EMI"
Stiching ground planes together around high speed signals absolutely helps with EMI and cross talk. Parallel planes that aren't stitched together aren't ground planes, they are wave guides.
Yes, I know. But if there aren't any high speeds signals it's a bit of a waste.
Common use for graphic card drivers etc.
Via stitching alongside the entire track does not make sense.
I have seen people (in professional companies) stitching every possible GND plane because "it would help against noise and EMI"
Stiching ground planes together around high speed signals absolutely helps with EMI and cross talk. Parallel planes that aren't stitched together aren't ground planes, they are wave guides.
Yes, I know. But if there aren't any high speeds signals it's a bit of a waste.
Common use for graphic card drivers etc.
An 1 MHz SPI clock signal coming from a simple microcontroller could have edges in the 5ns region. That's 200MHz. The 5th harmonics is in the Ghz region. Is that RF enough for you? Anyway, you are way off topic, answering to something that was two years ago.
Via stitching alongside the entire track does not make sense.
I have seen people (in professional companies) stitching every possible GND plane because "it would help against noise and EMI"
Stiching ground planes together around high speed signals absolutely helps with EMI and cross talk. Parallel planes that aren't stitched together aren't ground planes, they are wave guides.
Yes, I know. But if there aren't any high speeds signals it's a bit of a waste.
Common use for graphic card drivers etc.
An 1 MHz SPI clock signal coming from a simple microcontroller could have edges in the 5ns region. That's 200MHz. The 5th harmonics is in the Ghz region. Is that RF enough for you? Anyway, you are way off topic, answering to something that was two years ago.
Whoops, I didn't see that the specific post was that long ago! lol
I was not talking about 1Mhz SPI clocks btw
Basically that you conductivity is proportional the the cross sectional area of your condutor. If you punch a non conductive hole in it you have less copper. I'll admit there might be some combination of hole size and plating thickness that this idea doesn't hold for though.
Indeed, with 35um copper, 2 layer and 0.25mm(25um vias plating tickness) hole diameter, generally the amount of copper for of a PCB cross-section is improved. As the number of parallel layer increase and the copper thickness increase (es. 70um or 105um) vias stitching could also reduce the amount of copper for a PCB cross-section.